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Applied Materials presented a roadmap on how we might get to 3 nm using disappointingly conventional semiconductor processing techniques[0]. In short, you make
by gene-h 10y ago
Applied Materials presented a roadmap on how we might get to 3 nm using disappointingly conventional semiconductor processing techniques[0]. In short, you make the transistors tall and thin.
[0] https://web.archive.org/web/20130810001315/http://www.semiconwest.org/sites/semiconwest.org/files/docs/SW2013_Adam%20Brand_Applied%20Materials.pdf https://web.archive.org/web/20130810001315/http://www.semico...
- thoughtsimple 10y agoMaybe. Most of the presentation is beyond my knowledge level. But the 10nm & 7nm design is showing using a III-V FinFET. As far as I know, no one has that working yet. And as far as I can tell, this doesn't talk much about lithography. Multi patterning is reportedly going to be problem at 10nm and lower and EUV isn't ready yet either.