Here. 64-bit addition on RV32I. ; input 1 (msb r1, lsb r2) ; input 2 (r3, r4) ; output (r5, r6) xori r5, r4, -1 sltu r5, r5, r2

Here. 64-bit addition on RV32I. ; input 1 (msb r1, lsb r2) ; input 2 (r3, r4) ; output (r5, r6) xori r5, r4, -1 sltu r5, r5, r2 add r6, r4, r2 add r5, r5, r3 add r5, r5, r1 This is what I mean. Outside a few applications (mostly asymmetric crypto) nobody cares that it takes five instructions instead of two. Remember that this is the same processor that outright omits multiplication from the core spec.