> offer finer granularity than page allocations How the fuck would that work? Today, the page table is cached in a TLB and modern Intel processors only have 10

> offer finer granularity than page allocations How the fuck would that work? Today, the page table is cached in a TLB and modern Intel processors only have 1024 entries! If you have a new entry in the page table for every malloc, dereferencing virtual memory will require a page walk for pretty much every memory access. You can't cache millions of entries.