It's unfortunate he didn't touch more on the DEC Alpha AXP. It was designed from the start to be a 64-bit chip, unlike most 64-bit ISAs in use today. Sure, it

It's unfortunate he didn't touch more on the DEC Alpha AXP. It was designed from the start to be a 64-bit chip, unlike most 64-bit ISAs in use today. Sure, it took them a bit to be convinced that single-byte loads and stores were worthy of dedicated instructions. It was designed so that most of your kernel code wasn't actually running in a privileged CPU mode, but instead make upcalls to PAL code, a sort of super lightweight hypervisor that emulated how ever many of rings of protection the kernel needed. (Ultrix and Linux needed 2 rings. VMS ran on another set of firmware that emulated more rings.) It was a nice clean design that was running at 500 MHz back when Intel could manage 200 MHz. Its memory model was more friendly to parallel execution (and less friendly to compiler and JIT writers) than the x86 memory model, forcing weaker consistency guarantees out of the JVM memory model as a result. It seems a shame to me that the architecture was never revived. I'd like to hear more about its quirks and flaws.