In theory but not in practice. 24hr RTL to GDS has been the promise, but the design and process complexities keep growing. Depending on the complexity of the c

In theory but not in practice. 24hr RTL to GDS has been the promise, but the design and process complexities keep growing. Depending on the complexity of the chip, the backend process takes several months. It's an iterative process. A reasonable complex chip has to be split into several partitions. The size of the partition determines the turn around. In the designs that I have worked on, we try to limit the turnaround time (RTL->GDS) to be one week for the larger partitions. I would change your statement to say that the EDA vendors have created tools that allow Physical Design engineers to address the design challenges. It is still a gruelling, iterative, painstaking process.