Others mention SoC back-end as being separate from custom design, which is definitely true, but process has an impact on both. For custom digital design and So

Others mention SoC back-end as being separate from custom design, which is definitely true, but process has an impact on both. For custom digital design and SoC, you start with RTL. In custom design, you read the RTL and create a schematic using logic gates which implements the RTL spec. Generally, you have something to start with from the previous project, unless your block has seen massive changes. Then you floorplan the design, placing the interface and gates, and drawing the routes of the critical nets. Then you perform static timing analysis and many other checks to converge the design. This is a very iterative process, especially as some of your timing analysis depends on other blocks. (I don't have experience in analog, other than working closely with a few analog designers as a customer for some mixed-signal design I did a few years ago) Analog designers use similar tools to create schematics/netlist and physical design. The verification process is much different, with a lot of work going to developing simulations to ensure the circuit works as it needs to in a wide variety of conditions (process variation, operating voltage, and temperature). There's probably a lot of other stuff as well, but I am not privy to all they do. For SoC design, you compile RTL to netlist, using a logic synthesis tool. The synthesis tools are smart enough to approximate the physical design of the block, and you can refine your recipe to guide the synthesis tool to converge static timing in the netlist itself. Once that's complete you move to the automated place and route (APR) tools. Here you will spend some time and effort to floorplan your block: mostly placing of large sub-blocks and your pin interface to the rest of the SoC. Once you have that done, you'll go though placement, clock-tree synthesis, and routing, refining the recipe that will converge your design. Again, you will iterate on the design to converge static timing analysis and other checks. In both these cases you will also need to converge the physical design to meet the design rule checks. The automated tools available in both environments take the design rules into account, but the complexity of these rules is not fully understood by the automation, and so user intervention is required. Depending on your group, you may have a mask designer available to help with meeting process design rules, but most groups require the block owner to do the majority of work in this domain, with the mask designer available for final clean-up at tape-in. Hope this helps.