Intel has a roadmap down to 3nm, and I believe Imec does, as well. But the future is probably a combination of different packaging with faster interconnects and

Intel has a roadmap down to 3nm, and I believe Imec does, as well. But the future is probably a combination of different packaging with faster interconnects and better throughput to and from a variety of memory types. There are a couple of ways to drop the heat. One is a different transistor structure, which may allow for a sharp reduction in voltage (0.1 or 0.2 volts vs. 0.7 to 3.5V). The second way is to use silicon photonics between chips in a package, which is coming one of these days.