The "recompile" needs then to be extracted into another Verilog source code with all delays taken into account and all tests should pass on that extracted sourc

The "recompile" needs then to be extracted into another Verilog source code with all delays taken into account and all tests should pass on that extracted source. Then, if you are diligent enough, you execute static and dynamic analysis. One should know that for processes less than 90nm the shape of wire starts to play - delay begin to depend not only on the length of wire, but on the number of turns as well. All this means that the smaller the process, the more time and computing resources will be spent on post-synthesis, place and route stages.