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No, I don't think there is an easy solution. It is expensive for the foundry (TSMC, GlobalFoundries, Intel, Samsung, etc.) and it is also expensive for the EDA
by sweden 10y ago
No, I don't think there is an easy solution. It is expensive for the foundry (TSMC, GlobalFoundries, Intel, Samsung, etc.) and it is also expensive for the EDA companies that create all the necessary tools (Synopsys, Cadence and Mentor).
Even if the EDA companies were to provide all of the tools for free, the startups would be facing the high costs from the foundries.
But to tell you the truth, there is not much incentive to design in the newest node if you don't have money to spend. The technology not only is expensive but it is also unstable.
- adapteva 10y agoAgree that there will be less designs that need the advancing nodes (the number of apps needing 1B transistors per chip is limited), but there will be plenty of opportunities at the system level that warrant the $10M type investment needed.
- petra 10y agoIdk. The recent tsmc 16nm finfet process offers great leakage numbers (30pa/um) . coupled with packages that can manage extremly tiny packages like the one from tere-circuit could be really interesting , if it was affordable. Or the other option is to build multi for chips like marvel with their Lego concept offered, all at advanced nodes, but most of the dies after reused from previous designs.
- adapteva 10y agoimho, the only reason to go to 14nm and below is if you are pushing the envelope in terms of performance (HPC) or integration (smartphone). Everything else can probably stay at 28nm or above and be combined with 14-7nm using 2.5D or 3D package integration. Note that unless you are a Tier-1 system player you will "never" be able to get known good dies from a big fabless semi vendor, but taping out twice yourself and combining them yourself is pretty straightforward if you have a good packaging partner (like Amkor/ASE)