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Actually, nowadays even some parts of digital designs are full custom, meaning that they are designed manually at the silicon level. This is usually the case wi

by Cyph0n 11y ago

Actually, nowadays even some parts of digital designs are full custom, meaning that they are designed manually at the silicon level. This is usually the case with circuits that require high performance, such as adders, multipliers, etc. Also, you forgot to mention that memory is simply not synthesizable, so on-chip cache for example needs to have a full layout from scratch. Keep in mind that this is the case for Intel and not ARM. The latter uses standard cells, which means it's basically all synthesized. Source: my professor.

sweden 11y ago
The process of design digital circuits will depend of course from company to company, depending on the need of higher performance modules. But the fundamental of digital design is that everything is done using Verilog and the change of process node is completely transparent.
- moflome 11y ago
  You're ignoring the complexity of the back-end design process, actually laying out the RTL design is a massive issue at 10nm.
  - adapteva 11y ago
    If the cost of chip back-end is increasing exponentially from 65nm to 28nm to 14nm you are doing it wrong. (it's that simple). Since 0.25um, I have heard doom and gloom about how difficult "the next node" will be. So far it hasn't happened. If it does, I do agree that it's game over. So far the EDA companies and foundries have always come through.
    - nickpsecurity 11y ago
      It was that difficult. In my anti-subversion and OSS HW research, I've been collecting papers on EDA techniques and issues going back to the beginning so teams can build replacements for commercial tools over time. The reason it's not doom and gloom for the ASIC developer is that CompSci, EDA startups, and Big Three threw so many PhD's worth of thinking at each set of problems it isn't even funny. Talk about conquering chaos with human ingenuity every time a node shrinks. As you said, the EDA companies and foundries always came through. It was hard work, though. Work OSS will have to duplicate at least on EDA side.

by Cyph0n 11y ago

sweden 11y ago

The process of design digital circuits will depend of course from company to company, depending on the need of higher performance modules. But the fundamental of digital design is that everything is done using Verilog and the change of process node is completely transparent.

moflome 11y ago
You're ignoring the complexity of the back-end design process, actually laying out the RTL design is a massive issue at 10nm.
- adapteva 11y ago
  If the cost of chip back-end is increasing exponentially from 65nm to 28nm to 14nm you are doing it wrong. (it's that simple). Since 0.25um, I have heard doom and gloom about how difficult "the next node" will be. So far it hasn't happened. If it does, I do agree that it's game over. So far the EDA companies and foundries have always come through.
  - nickpsecurity 11y ago
    It was that difficult. In my anti-subversion and OSS HW research, I've been collecting papers on EDA techniques and issues going back to the beginning so teams can build replacements for commercial tools over time. The reason it's not doom and gloom for the ASIC developer is that CompSci, EDA startups, and Big Three threw so many PhD's worth of thinking at each set of problems it isn't even funny. Talk about conquering chaos with human ingenuity every time a node shrinks. As you said, the EDA companies and foundries always came through. It was hard work, though. Work OSS will have to duplicate at least on EDA side.