No, it's not only for mixed-signal IPs (unfortunately). It's also for soft IPs, in Verilog. When you start from Verilog you still have to do the back-end work,

No, it's not only for mixed-signal IPs (unfortunately). It's also for soft IPs, in Verilog. When you start from Verilog you still have to do the back-end work, to meet timing constraints. Only "hard macros" IPs requires no back-end work, as the work has already been done by the IP provider for a very specific process. If you have a soft IP (Verilog) on the other hand, which are portable across nodes, the back-end work is for the SoC vendor to do. And yes, the IP design can make this more or less easy, but there's still work to do, and this back-end work gets heavier and heavier with more advanced nodes.