You nearly got it, it is being "hand-stitched" but with lasers. It's the way the chips are etched with lasers (patterning) that is driving most of the costs. T

You nearly got it, it is being "hand-stitched" but with lasers. It's the way the chips are etched with lasers (patterning) that is driving most of the costs. The lasers have a limit of how small it can get and the smaller the chips get, the more you have to re-etch with different materials (for the laser to go through) to get it to where you want it, which also increases the amount of defects that will happen on the chip, driving up the testing costs as well. 28nm was the limit with a single pattern design. 20nm required a double-pattern and certain 10nm/7nm designs will need triple or quad-patterns which is super expensive and slows down the process. That's what the article meant with this statement: > But at 7nm, optical and multi-patterning are simply too complex and expensive, at least according to Samsung. So to make 7nm cost effective, it makes more sense to wait for EUV. In theory, EUV can simplify the patterning process. You can find more information here: http://www.anandtech.com/show/10272/samsung-foundry-updates-7nm-euv-10lpp-and-14lpc http://www.anandtech.com/show/10272/samsung-foundry-updates-... This might help as well: http://www.extremetech.com/computing/160509-seeing-double-tsmc-adopts-new-lithography-technique-to-push-moores-law-to-20nm http://www.extremetech.com/computing/160509-seeing-double-ts...