13 ms·

If you are speaking of the digital designs, yes, what you say is absolutely right. But you need to keep in mind the analog designs. While a typical CPU, a typi

by sweden 10y ago

If you are speaking of the digital designs, yes, what you say is absolutely right. But you need to keep in mind the analog designs. While a typical CPU, a typical GPU or a typical cryptographic IP chip (for a example) can be developed in just Verilog since they are just pure logic, when you move to the Mixed Signal IP, you can't use only Verilog, you have to manually design parts of the chip (creating the schematics of the designs at the transistor level and converting them to layouts). Examples of mixed signal IP are USB, HDMI, MIPI, Ethernet, PCIe, and so on. We don't have tools capable of synthetizing really fast PLLs, DCOs, Band Gaps, most of the high speed analog blocks. But I think the article was exaggerating on the "50 engineers will need 10 years to complete the chip design to tape-out". I work at Synopsys and we are already working on the latest process nodes (10nm, 7nm, 5 nm) and we already have some solutions ready for silicon and it didn't took us 10 years. All these articles make it sound so dramatic that it's nowhere near the reality. The process of designing the analog blocks again in 10nm, 7nm, 5 nm and so on, it's exactly the same every time. It is very much like porting your C++ code to Python: sure you have to do it from scratch but the process and the fundamental concepts are exactly the same. It's not rocket science nor quantum physics, it's easier than it sounds. The main problem is the huge cost of the tools and of the technology from the foundry. If you are past that, you just need time and some knowledge in micro-electronics. Don't be fooled by these over dramatic articles, the hard part of digital and analog design is not getting the knowledge to do it, it's getting the money to have the proper tools to do it.

bhouston 10y ago
Great response. Got a question for you then: are we actually hitting the end of Moore's law here or are we just before a new technology transition for CPUs, such as away from silicon.
- sweden 10y ago
  We are indeed hitting the end of Moore's law. The companies that provide IP are watching the market splitting into two: the companies that want the latest process node to show off technology (for example, Apple, Samsung, Huawei, etc) and the companies that want older but stable process nodes (IoT companies and the automotive industry). When most of the articles speak of the newest process nodes (for example, the 5nm process node) they only touch the economics part of it: "it's expensive, it's costly". But they don't mention the many problems that come with it: it's unstable, there is much more current leakage which increases power consumption unexpectedly, it is not suitable for long longevity and the architecture of your analog blocks have to take into account all these problems which don't exist in the older process nodes. It is possible to produce solutions in 5 nm, but the question is no longer about if we can do it or not. The downsides os these nodes go beyond the engineering resources and the economic resources that are needed to achieve them. That is why the automotive industry is not interesting in these kind of nodes. They want the stable and cheap nodes like 28nm and 40nm, they know that these nodes are well tested and have long longevity. We are also reaching a point in which we already have enough advanced technology for our needs, we need to start to get rid of the need of reaching the next process node in order to have better hardware.
- yaantc 10y ago
  There's no single answer here. First, Moore's law is about the density of the least cost process doubling every N months (N changed over time ;). So cost is a key part of Moore's law. When you talk about cost, there are fixed NRE paid once per chip design, and then marginal cost per transistor (just including production). To get the full view, it's logical to consider a "fully loaded" cost per transistor, where you also amortize the fixed NRE expense taking into account the expected number of produces chips for a given design. And that's where the increasing NREs bite and make a difference. Even when the marginal production cost per transistor decreases, to benefit from that cost decrease one must have sufficient chip production volume to amortize the NRE and still benefit from a cost decrease. With exploding NREs on more advanced nodes, this requires ever higher volume production to benefit from lower costs on more advanced nodes. At this stage, if you're a medium chip vendor Moore's law is already over --- because with small volume the NRE leads to an increase in total cost per transistor for newer processes. Vendors like Broadcom and NVidia complained publicly about the end of Moore's law, so we're not talking small volume either. For very large volumes, it may still be going on. But that's hard to tell. At some point, the cost may go up even for the biggest (Apple, Intel, Qualcomm) but they may still push forward a bit for improved performance --- meaning higher power efficiency --- as long as there are enough people willing to pay for it. It's no longer Moore's law (where you get more for less money), but it's still moving onto more advanced processes. Still, even assuming enough people are willing to pay more for improved performance (a big assumption IMHO) there are quite formidable challenges ahead.
Cyph0n 10y ago
Actually, nowadays even some parts of digital designs are full custom, meaning that they are designed manually at the silicon level. This is usually the case with circuits that require high performance, such as adders, multipliers, etc. Also, you forgot to mention that memory is simply not synthesizable, so on-chip cache for example needs to have a full layout from scratch. Keep in mind that this is the case for Intel and not ARM. The latter uses standard cells, which means it's basically all synthesized. Source: my professor.
- sweden 10y ago
  The process of design digital circuits will depend of course from company to company, depending on the need of higher performance modules. But the fundamental of digital design is that everything is done using Verilog and the change of process node is completely transparent.
  - moflome 10y ago
    You're ignoring the complexity of the back-end design process, actually laying out the RTL design is a massive issue at 10nm.
    - adapteva 10y ago
      If the cost of chip back-end is increasing exponentially from 65nm to 28nm to 14nm you are doing it wrong. (it's that simple). Since 0.25um, I have heard doom and gloom about how difficult "the next node" will be. So far it hasn't happened. If it does, I do agree that it's game over. So far the EDA companies and foundries have always come through.
      - nickpsecurity 10y ago
        It was that difficult. In my anti-subversion and OSS HW research, I've been collecting papers on EDA techniques and issues going back to the beginning so teams can build replacements for commercial tools over time. The reason it's not doom and gloom for the ASIC developer is that CompSci, EDA startups, and Big Three threw so many PhD's worth of thinking at each set of problems it isn't even funny. Talk about conquering chaos with human ingenuity every time a node shrinks. As you said, the EDA companies and foundries always came through. It was hard work, though. Work OSS will have to duplicate at least on EDA side.
petra 10y ago
In many places engineers complain about the high NRE costs.Do you as someone from the inside see a solution, in the future, leading for a startup to be able to design with the newest node ?
- sweden 10y ago
  No, I don't think there is an easy solution. It is expensive for the foundry (TSMC, GlobalFoundries, Intel, Samsung, etc.) and it is also expensive for the EDA companies that create all the necessary tools (Synopsys, Cadence and Mentor). Even if the EDA companies were to provide all of the tools for free, the startups would be facing the high costs from the foundries. But to tell you the truth, there is not much incentive to design in the newest node if you don't have money to spend. The technology not only is expensive but it is also unstable.
  - adapteva 10y ago
    Agree that there will be less designs that need the advancing nodes (the number of apps needing 1B transistors per chip is limited), but there will be plenty of opportunities at the system level that warrant the $10M type investment needed.
    - petra 10y ago
      Idk. The recent tsmc 16nm finfet process offers great leakage numbers (30pa/um) . coupled with packages that can manage extremly tiny packages like the one from tere-circuit could be really interesting , if it was affordable. Or the other option is to build multi for chips like marvel with their Lego concept offered, all at advanced nodes, but most of the dies after reused from previous designs.
      - adapteva 10y ago
        imho, the only reason to go to 14nm and below is if you are pushing the envelope in terms of performance (HPC) or integration (smartphone). Everything else can probably stay at 28nm or above and be combined with 14-7nm using 2.5D or 3D package integration. Note that unless you are a Tier-1 system player you will "never" be able to get known good dies from a big fabless semi vendor, but taping out twice yourself and combining them yourself is pretty straightforward if you have a good packaging partner (like Amkor/ASE)
esmi 10y ago
I definitely agree with the overall sentiment of your post but don't forget; even pure digital designs need to be powered and cooled and the design problems and available solutions for doing this at 28nm vs 10/7/5nm are different.

by sweden 10y ago

bhouston 10y ago

Great response. Got a question for you then: are we actually hitting the end of Moore's law here or are we just before a new technology transition for CPUs, such as away from silicon.

sweden 10y ago
We are indeed hitting the end of Moore's law. The companies that provide IP are watching the market splitting into two: the companies that want the latest process node to show off technology (for example, Apple, Samsung, Huawei, etc) and the companies that want older but stable process nodes (IoT companies and the automotive industry). When most of the articles speak of the newest process nodes (for example, the 5nm process node) they only touch the economics part of it: "it's expensive, it's costly". But they don't mention the many problems that come with it: it's unstable, there is much more current leakage which increases power consumption unexpectedly, it is not suitable for long longevity and the architecture of your analog blocks have to take into account all these problems which don't exist in the older process nodes. It is possible to produce solutions in 5 nm, but the question is no longer about if we can do it or not. The downsides os these nodes go beyond the engineering resources and the economic resources that are needed to achieve them. That is why the automotive industry is not interesting in these kind of nodes. They want the stable and cheap nodes like 28nm and 40nm, they know that these nodes are well tested and have long longevity. We are also reaching a point in which we already have enough advanced technology for our needs, we need to start to get rid of the need of reaching the next process node in order to have better hardware.
yaantc 10y ago
There's no single answer here. First, Moore's law is about the density of the least cost process doubling every N months (N changed over time ;). So cost is a key part of Moore's law. When you talk about cost, there are fixed NRE paid once per chip design, and then marginal cost per transistor (just including production). To get the full view, it's logical to consider a "fully loaded" cost per transistor, where you also amortize the fixed NRE expense taking into account the expected number of produces chips for a given design. And that's where the increasing NREs bite and make a difference. Even when the marginal production cost per transistor decreases, to benefit from that cost decrease one must have sufficient chip production volume to amortize the NRE and still benefit from a cost decrease. With exploding NREs on more advanced nodes, this requires ever higher volume production to benefit from lower costs on more advanced nodes. At this stage, if you're a medium chip vendor Moore's law is already over --- because with small volume the NRE leads to an increase in total cost per transistor for newer processes. Vendors like Broadcom and NVidia complained publicly about the end of Moore's law, so we're not talking small volume either. For very large volumes, it may still be going on. But that's hard to tell. At some point, the cost may go up even for the biggest (Apple, Intel, Qualcomm) but they may still push forward a bit for improved performance --- meaning higher power efficiency --- as long as there are enough people willing to pay for it. It's no longer Moore's law (where you get more for less money), but it's still moving onto more advanced processes. Still, even assuming enough people are willing to pay more for improved performance (a big assumption IMHO) there are quite formidable challenges ahead.

Cyph0n 10y ago

Actually, nowadays even some parts of digital designs are full custom, meaning that they are designed manually at the silicon level. This is usually the case with circuits that require high performance, such as adders, multipliers, etc. Also, you forgot to mention that memory is simply not synthesizable, so on-chip cache for example needs to have a full layout from scratch. Keep in mind that this is the case for Intel and not ARM. The latter uses standard cells, which means it's basically all synthesized. Source: my professor.

sweden 10y ago
The process of design digital circuits will depend of course from company to company, depending on the need of higher performance modules. But the fundamental of digital design is that everything is done using Verilog and the change of process node is completely transparent.
- moflome 10y ago
  You're ignoring the complexity of the back-end design process, actually laying out the RTL design is a massive issue at 10nm.
  - adapteva 10y ago
    If the cost of chip back-end is increasing exponentially from 65nm to 28nm to 14nm you are doing it wrong. (it's that simple). Since 0.25um, I have heard doom and gloom about how difficult "the next node" will be. So far it hasn't happened. If it does, I do agree that it's game over. So far the EDA companies and foundries have always come through.
    - nickpsecurity 10y ago
      It was that difficult. In my anti-subversion and OSS HW research, I've been collecting papers on EDA techniques and issues going back to the beginning so teams can build replacements for commercial tools over time. The reason it's not doom and gloom for the ASIC developer is that CompSci, EDA startups, and Big Three threw so many PhD's worth of thinking at each set of problems it isn't even funny. Talk about conquering chaos with human ingenuity every time a node shrinks. As you said, the EDA companies and foundries always came through. It was hard work, though. Work OSS will have to duplicate at least on EDA side.

petra 10y ago

In many places engineers complain about the high NRE costs.Do you as someone from the inside see a solution, in the future, leading for a startup to be able to design with the newest node ?

sweden 10y ago
No, I don't think there is an easy solution. It is expensive for the foundry (TSMC, GlobalFoundries, Intel, Samsung, etc.) and it is also expensive for the EDA companies that create all the necessary tools (Synopsys, Cadence and Mentor). Even if the EDA companies were to provide all of the tools for free, the startups would be facing the high costs from the foundries. But to tell you the truth, there is not much incentive to design in the newest node if you don't have money to spend. The technology not only is expensive but it is also unstable.
- adapteva 10y ago
  Agree that there will be less designs that need the advancing nodes (the number of apps needing 1B transistors per chip is limited), but there will be plenty of opportunities at the system level that warrant the $10M type investment needed.
  - petra 10y ago
    Idk. The recent tsmc 16nm finfet process offers great leakage numbers (30pa/um) . coupled with packages that can manage extremly tiny packages like the one from tere-circuit could be really interesting , if it was affordable. Or the other option is to build multi for chips like marvel with their Lego concept offered, all at advanced nodes, but most of the dies after reused from previous designs.
    - adapteva 10y ago
      imho, the only reason to go to 14nm and below is if you are pushing the envelope in terms of performance (HPC) or integration (smartphone). Everything else can probably stay at 28nm or above and be combined with 14-7nm using 2.5D or 3D package integration. Note that unless you are a Tier-1 system player you will "never" be able to get known good dies from a big fabless semi vendor, but taping out twice yourself and combining them yourself is pretty straightforward if you have a good packaging partner (like Amkor/ASE)

esmi 10y ago

I definitely agree with the overall sentiment of your post but don't forget; even pure digital designs need to be powered and cooled and the design problems and available solutions for doing this at 28nm vs 10/7/5nm are different.