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It means you live inside cadence actually drawing where metal will go, where poly will go and so on, you design the actual transistors, connections, everything.
by vasco 11y ago
It means you live inside cadence actually drawing where metal will go, where poly will go and so on, you design the actual transistors, connections, everything. You do this design and you're constantly fixing warnings and errors about process limitations such as "this metal line can't be thinner than X amount", or "on level 3 you can't have this interconnect so closer together" and so on. Looks more or less like this: http://i.imgur.com/ECIVChO.png http://i.imgur.com/ECIVChO.png
- petra 11y agoThanks. But how does it Apply to a whole SOC ? you basically go to the critical sections and optimize them by hand, better than the synthesis tool ? Or just supply some basic components to the design team , and if so isn't it the job of the fab and the PDK(process design kit) ?
- sweden 11y agoI'm not the OP, but the same does not apply to the SoC. What the OP showed you applies only to the Mixed-Signal IP, when you have a Digital part (developed in Verilog) and an Analog part (developed in tools like the OP showed). When you start building a SoC, you will build it like you would be building a Lego: you contact the various IP providers (Synopsys, Cadence, ARM, Imagination technologies, etc) and you start buying IP for the CPU, for the HDMI chip, for the memory (DDR), and so on, and then you put them together. The IP providers are responsible for making sure that you receive the layout of the IPs working for a certain process node. If you are just building the SoC, you won't need to look at the schematics or at the layout.
- yaantc 11y agoNo, it's not only for mixed-signal IPs (unfortunately). It's also for soft IPs, in Verilog. When you start from Verilog you still have to do the back-end work, to meet timing constraints. Only "hard macros" IPs requires no back-end work, as the work has already been done by the IP provider for a very specific process. If you have a soft IP (Verilog) on the other hand, which are portable across nodes, the back-end work is for the SoC vendor to do. And yes, the IP design can make this more or less easy, but there's still work to do, and this back-end work gets heavier and heavier with more advanced nodes.
- sweden 11y agoYes, of course that the Place&Route part requires some work at the layout level, but it's not like you are going to place your transistors by hand after the synthesis tool produces a netlist.
- kolinko 11y agoIs there a chance of there being better / more automated tools?
- solnyshok 11y agoany Y startups in this area?
- typon 11y agoThese aren't simple 'apps'. These tools solve several NP complete problems, with decades of research in algorithms behind them. It is near impossible for a startup to compete with Cadence. Most startups are just plugins to Cadence that improve a tiny part of the flow, usually written in SKILL. And when they get good enough, Cadence acquires them.
- petra 11y agoI think this area is controlled by a 2-3 big companies so it depends how they enable and accept startups. Building all the tools is very challenging - very large investments, maybe in the billions.
- nickpsecurity 11y agoMentor, the little guy, was spending around $300-400 million a year on R&D. They also often acquire research and tooling from CompSci much to my irritation given I'm digging it up for OSS EDA purposes. So, yeah, ridiculously huge investments.
- williadc 11y agoThe tools improve steadily, but the complexity of the designs themselves, and the process design rules are also increasing. Cadence and Synopsys (the two biggest EDA vendors) have both released major new versions of their automated place and route tools, with major improvements. However, 10nm presents new types of restrictions that need to be modeled and accounted for.
- williadc 11y agoIs that wrong-way poly? I haven't seen that in years!