4 ms·

Your mental model only covers the front-end of design. The back-end, where I work, is very dependant on process. You must update the design to take advantage of

Your mental model only covers the front-end of design. The back-end, where I work, is very dependant on process. You must update the design to take advantage of process improvements (otherwise why bother moving?), and the new process comes with new restrictions for placing transistors and interconnect that must be accounted for.

petra 10y ago
Your part of the process is a mystery relative to the front end - which is similar to fpga design. Can you explain/link to how your work process looks like ?
- vasco 10y ago
  It means you live inside cadence actually drawing where metal will go, where poly will go and so on, you design the actual transistors, connections, everything. You do this design and you're constantly fixing warnings and errors about process limitations such as "this metal line can't be thinner than X amount", or "on level 3 you can't have this interconnect so closer together" and so on. Looks more or less like this: http://i.imgur.com/ECIVChO.png http://i.imgur.com/ECIVChO.png
  - petra 10y ago
    Thanks. But how does it Apply to a whole SOC ? you basically go to the critical sections and optimize them by hand, better than the synthesis tool ? Or just supply some basic components to the design team , and if so isn't it the job of the fab and the PDK(process design kit) ?
    - sweden 10y ago
      I'm not the OP, but the same does not apply to the SoC. What the OP showed you applies only to the Mixed-Signal IP, when you have a Digital part (developed in Verilog) and an Analog part (developed in tools like the OP showed). When you start building a SoC, you will build it like you would be building a Lego: you contact the various IP providers (Synopsys, Cadence, ARM, Imagination technologies, etc) and you start buying IP for the CPU, for the HDMI chip, for the memory (DDR), and so on, and then you put them together. The IP providers are responsible for making sure that you receive the layout of the IPs working for a certain process node. If you are just building the SoC, you won't need to look at the schematics or at the layout.
      - yaantc 10y ago
        No, it's not only for mixed-signal IPs (unfortunately). It's also for soft IPs, in Verilog. When you start from Verilog you still have to do the back-end work, to meet timing constraints. Only "hard macros" IPs requires no back-end work, as the work has already been done by the IP provider for a very specific process. If you have a soft IP (Verilog) on the other hand, which are portable across nodes, the back-end work is for the SoC vendor to do. And yes, the IP design can make this more or less easy, but there's still work to do, and this back-end work gets heavier and heavier with more advanced nodes.
        sweden 10y ago
        Yes, of course that the Place&Route part requires some work at the layout level, but it's not like you are going to place your transistors by hand after the synthesis tool produces a netlist.
  - kolinko 10y ago
    Is there a chance of there being better / more automated tools?
    - solnyshok 10y ago
      any Y startups in this area?
      - typon 10y ago
        These aren't simple 'apps'. These tools solve several NP complete problems, with decades of research in algorithms behind them. It is near impossible for a startup to compete with Cadence. Most startups are just plugins to Cadence that improve a tiny part of the flow, usually written in SKILL. And when they get good enough, Cadence acquires them.
    - petra 10y ago
      I think this area is controlled by a 2-3 big companies so it depends how they enable and accept startups. Building all the tools is very challenging - very large investments, maybe in the billions.
      - nickpsecurity 10y ago
        Mentor, the little guy, was spending around $300-400 million a year on R&D. They also often acquire research and tooling from CompSci much to my irritation given I'm digging it up for OSS EDA purposes. So, yeah, ridiculously huge investments.
    - williadc 10y ago
      The tools improve steadily, but the complexity of the designs themselves, and the process design rules are also increasing. Cadence and Synopsys (the two biggest EDA vendors) have both released major new versions of their automated place and route tools, with major improvements. However, 10nm presents new types of restrictions that need to be modeled and accounted for.
  - williadc 10y ago
    Is that wrong-way poly? I haven't seen that in years!
- williadc 10y ago
  Others mention SoC back-end as being separate from custom design, which is definitely true, but process has an impact on both. For custom digital design and SoC, you start with RTL. In custom design, you read the RTL and create a schematic using logic gates which implements the RTL spec. Generally, you have something to start with from the previous project, unless your block has seen massive changes. Then you floorplan the design, placing the interface and gates, and drawing the routes of the critical nets. Then you perform static timing analysis and many other checks to converge the design. This is a very iterative process, especially as some of your timing analysis depends on other blocks. (I don't have experience in analog, other than working closely with a few analog designers as a customer for some mixed-signal design I did a few years ago) Analog designers use similar tools to create schematics/netlist and physical design. The verification process is much different, with a lot of work going to developing simulations to ensure the circuit works as it needs to in a wide variety of conditions (process variation, operating voltage, and temperature). There's probably a lot of other stuff as well, but I am not privy to all they do. For SoC design, you compile RTL to netlist, using a logic synthesis tool. The synthesis tools are smart enough to approximate the physical design of the block, and you can refine your recipe to guide the synthesis tool to converge static timing in the netlist itself. Once that's complete you move to the automated place and route (APR) tools. Here you will spend some time and effort to floorplan your block: mostly placing of large sub-blocks and your pin interface to the rest of the SoC. Once you have that done, you'll go though placement, clock-tree synthesis, and routing, refining the recipe that will converge your design. Again, you will iterate on the design to converge static timing analysis and other checks. In both these cases you will also need to converge the physical design to meet the design rule checks. The automated tools available in both environments take the design rules into account, but the complexity of these rules is not fully understood by the automation, and so user intervention is required. Depending on your group, you may have a mask designer available to help with meeting process design rules, but most groups require the block owner to do the majority of work in this domain, with the mask designer available for final clean-up at tape-in. Hope this helps.
deleted 10y ago
[deleted]

petra 10y ago

Your part of the process is a mystery relative to the front end - which is similar to fpga design. Can you explain/link to how your work process looks like ?

vasco 10y ago
It means you live inside cadence actually drawing where metal will go, where poly will go and so on, you design the actual transistors, connections, everything. You do this design and you're constantly fixing warnings and errors about process limitations such as "this metal line can't be thinner than X amount", or "on level 3 you can't have this interconnect so closer together" and so on. Looks more or less like this: http://i.imgur.com/ECIVChO.png http://i.imgur.com/ECIVChO.png
- petra 10y ago
  Thanks. But how does it Apply to a whole SOC ? you basically go to the critical sections and optimize them by hand, better than the synthesis tool ? Or just supply some basic components to the design team , and if so isn't it the job of the fab and the PDK(process design kit) ?
  - sweden 10y ago
    I'm not the OP, but the same does not apply to the SoC. What the OP showed you applies only to the Mixed-Signal IP, when you have a Digital part (developed in Verilog) and an Analog part (developed in tools like the OP showed). When you start building a SoC, you will build it like you would be building a Lego: you contact the various IP providers (Synopsys, Cadence, ARM, Imagination technologies, etc) and you start buying IP for the CPU, for the HDMI chip, for the memory (DDR), and so on, and then you put them together. The IP providers are responsible for making sure that you receive the layout of the IPs working for a certain process node. If you are just building the SoC, you won't need to look at the schematics or at the layout.
    - yaantc 10y ago
      No, it's not only for mixed-signal IPs (unfortunately). It's also for soft IPs, in Verilog. When you start from Verilog you still have to do the back-end work, to meet timing constraints. Only "hard macros" IPs requires no back-end work, as the work has already been done by the IP provider for a very specific process. If you have a soft IP (Verilog) on the other hand, which are portable across nodes, the back-end work is for the SoC vendor to do. And yes, the IP design can make this more or less easy, but there's still work to do, and this back-end work gets heavier and heavier with more advanced nodes.
      - sweden 10y ago
        Yes, of course that the Place&Route part requires some work at the layout level, but it's not like you are going to place your transistors by hand after the synthesis tool produces a netlist.
- kolinko 10y ago
  Is there a chance of there being better / more automated tools?
  - solnyshok 10y ago
    any Y startups in this area?
    - typon 10y ago
      These aren't simple 'apps'. These tools solve several NP complete problems, with decades of research in algorithms behind them. It is near impossible for a startup to compete with Cadence. Most startups are just plugins to Cadence that improve a tiny part of the flow, usually written in SKILL. And when they get good enough, Cadence acquires them.
  - petra 10y ago
    I think this area is controlled by a 2-3 big companies so it depends how they enable and accept startups. Building all the tools is very challenging - very large investments, maybe in the billions.
    - nickpsecurity 10y ago
      Mentor, the little guy, was spending around $300-400 million a year on R&D. They also often acquire research and tooling from CompSci much to my irritation given I'm digging it up for OSS EDA purposes. So, yeah, ridiculously huge investments.
  - williadc 10y ago
    The tools improve steadily, but the complexity of the designs themselves, and the process design rules are also increasing. Cadence and Synopsys (the two biggest EDA vendors) have both released major new versions of their automated place and route tools, with major improvements. However, 10nm presents new types of restrictions that need to be modeled and accounted for.
- williadc 10y ago
  Is that wrong-way poly? I haven't seen that in years!
williadc 10y ago
Others mention SoC back-end as being separate from custom design, which is definitely true, but process has an impact on both. For custom digital design and SoC, you start with RTL. In custom design, you read the RTL and create a schematic using logic gates which implements the RTL spec. Generally, you have something to start with from the previous project, unless your block has seen massive changes. Then you floorplan the design, placing the interface and gates, and drawing the routes of the critical nets. Then you perform static timing analysis and many other checks to converge the design. This is a very iterative process, especially as some of your timing analysis depends on other blocks. (I don't have experience in analog, other than working closely with a few analog designers as a customer for some mixed-signal design I did a few years ago) Analog designers use similar tools to create schematics/netlist and physical design. The verification process is much different, with a lot of work going to developing simulations to ensure the circuit works as it needs to in a wide variety of conditions (process variation, operating voltage, and temperature). There's probably a lot of other stuff as well, but I am not privy to all they do. For SoC design, you compile RTL to netlist, using a logic synthesis tool. The synthesis tools are smart enough to approximate the physical design of the block, and you can refine your recipe to guide the synthesis tool to converge static timing in the netlist itself. Once that's complete you move to the automated place and route (APR) tools. Here you will spend some time and effort to floorplan your block: mostly placing of large sub-blocks and your pin interface to the rest of the SoC. Once you have that done, you'll go though placement, clock-tree synthesis, and routing, refining the recipe that will converge your design. Again, you will iterate on the design to converge static timing analysis and other checks. In both these cases you will also need to converge the physical design to meet the design rule checks. The automated tools available in both environments take the design rules into account, but the complexity of these rules is not fully understood by the automation, and so user intervention is required. Depending on your group, you may have a mask designer available to help with meeting process design rules, but most groups require the block owner to do the majority of work in this domain, with the mask designer available for final clean-up at tape-in. Hope this helps.

deleted 10y ago

[deleted]