It's going to be a very interesting space, IMO. The thing about FPGAs is that they are deeply dependant on storage technology. Right now their gate configurat

It's going to be a very interesting space, IMO. The thing about FPGAs is that they are deeply dependant on storage technology. Right now their gate configuration is kept in SRAM loaded in at boot, which is the worst of all worlds. Not only is it non-volatile, it's very power hungry and takes up more than half of the space on the chip. And flash memory hasn't helped much because (from what I've been able to figure out) having tiny sections of flash for each logic element is impractical due to the physics of how it works. However, flash and SRAM aren't the end of the line, and advances in non-volatile memory will disproportionately affect FGPAs. It seems almost inevitable to me that the NVM landscape will be changing soon: several technologies are being worked on in parallel (e.g. NRAM and RRAM) - one of them is going to win, there's just too much demand for higher performance storage. When that happens, FPGAs will get to draft behind the huge tech investment made for the sake of SSDs etc. FPGAs with tiny NVM will look a lot more like structured ASICs (a prefabbed grid of gates, with a custom metal interconnect layer) than their current form. Instead of needing ~10x power and supporting ~1/4 the clock speeds, it'd be about half as fast and twice the power - still not ideal, but within spitting distance of the advantages of FPGAs outweighing the disadvantages vs. ASICs, and certainly a qualitative difference from where we're at today. This, combined with having the same thoughts as you about the criticalness to open computing, has gotten me to start working on improving the tooling for people just getting into FPGAs. It's hard to have an openness-based movement when there's not enough people, and it's hard to get people in if the first rung of the ladder's too high (e.g. installing a grab-bag of software and learning Verilog as step #1). Here's my (very alpha) work so far: http://blinklight.io http://blinklight.io (I haven't publicized it yet because I'm going to be doing a big change to the pitch/target market soon). I'm well aware of the limitations of visual programming, but I think it's an excellent basis for developing intuition before moving on to HDLs (especially for people coming from software who are thrown off by Verilog's superficial similarities to C).