14 ms·
10nm versus 7nm
- aexaey 11y agoWait, did I read this right - Intel is going to be the last one to get 10nm? > Samsung, for one, plans to ship its 10nm finFET technology by year’s end. > TSMC will move into 10nm production in early 2017 > Intel will move into 10nm production by mid-2017
- hyperpallium 11y ago> It’s now becoming clear that what other companies call a ‘10nm’ technology will not be as dense as Intel’s 10nm technology.
- eloff 11y agoYes, that's what a lay reading gets you - and why I was disappointed with the article. Is the author just clueless or are they trying to make one of Intel's competitors look better? Everyone who follows these things knows that the other guy's 14nm node is more comparable to Intel's 22nm node. Apparently a nanometer is not always a nanometer...
- petra 11y agoI think this journal aims to professional who know the details about intel/others process nodes, so he doesn't mention that specifically.
- i73668012 11y agoThe only thing you should be disappointed with is your reading comprehension. There are three paragraphs dedicated to your complaint. >“Not all 10nm technologies are the same,” said Mark Bohr, a senior fellow and director of process architecture and integration at Intel. “It’s now becoming clear that what other companies call a ‘10nm’ technology will not be as dense as Intel’s 10nm technology. We expect that what others call ‘7nm’ will be close to Intel’s 10nm technology for density.” >It wasn’t always like that. Traditionally, chipmakers scaled the key transistor specs by 0.7X at each node. This, in turn, roughly doubles the transistor density at each node. >Intel continues to follow this formula. At 16nm/14nm, though, others deviated from the equation from a density standpoint. For example, foundry vendors introduced finFETs at 16nm/14nm, but it incorporated a 20nm interconnect scheme.
- zaroth 11y agoWould upvote but for your first sentence.
- eloff 11y agoMissed that, I withdraw my complaint. The snark is not necessary though, not everyone has time to read the entire article, I read the top and skimmed the rest.
- testrun 11y agoAnd you start your comment with: Yes, that's what a lay reading gets you - and why I was disappointed with the article.
- MichaelBurge 11y ago> Then, there is the cost-driven decision. This is for foundry customers who may have lower volume products. They may not recoup their investment at 10nm. So, it makes more sense for them to skip 10nm and move to 7nm. Why is it cheaper to design a 7nm chip for a given performance than to design a 10nm chip? The article mentions the yields on newer processes are lower, so I would've expected them to be the performance option not the cost option.
- dboreham 11y agoCost is often driven by #die/wafer, which in turn is driven by die size which in turn is (often) driven by feature size.
- petra 11y agoNot an expert, but even if it was only a recompile, the development tools and fabrication masks are a decent share of the development costs, tens of millions.
- quickaccount 11y agoIt isn't. But if you move straight to 7nm you only need to recoup the costs for 7nm, not 10nm + 7nm.
- dmarcos 11y agoI've been following the semiconductor news in the last year closer than ever before. It really feels that the 7nm node will be the end of Moore's law. As a software engineer it intrigues me the constrains is going to impose to our craft in the next decade. We've been riding the performance exponential growth that allowed us to be sloppy programmers and still produce increasingly complex software. I work on the VR space and the conventional wisdom is that headsets and GPUs are going to get drastically smaller and powerful every year. I think this is not a given anymore and as a software practitioners we will have to step up the game and be much more careful about using resources. How is the end of Moore's low going to affect the cost of Software Development? The top software companies will be those that best use the hardware. Performance optimizations usually makes software more complex and increases the rigor you operate in. Many people have been able to got from 0 to make relevant contributions after learning programming in a few months or going through a coding bootcamp. That might get harder and harder since you will need deeper knowledge to produce competitive software. Is this going to increase the barrier of entry for developers? Is the developer pool going to shrink? Salaries go up? Is it going to be more a and more expensive to produce competitive software? Will it make software startups more capital intensive, since gluing 4 pieces of existing code around a good idea won't be enough to be successful?
- petra 11y agoTo some extent the mobile platform did the same thing:increasing the constraints, both on performance, and on interfaces. So maybe we'll see something similar ? more demand, higher salaries, but non the less, options for relative noobs to do interesting things ?
- kolinko 11y ago"Nonetheless", ftfy. Sorry for nitpicking.
- thesz 11y agoMoore law is about number of transistors per chip (IC). You can make transistors smaller, you can make chips larger, you can stack chips and you can make integrated circuits from several parts. I think your feeling is wrong.
- kbob 11y ago> “It will take chip designers about 500 man-years to bring out a mid-range 7nm SoC to production,” Gartner’s Wang said. Therefore, a team of 50 engineers will need 10 years to complete the chip design to tape-out. In comparison, it could take 300 engineer-years to bring out a 10nm device, 200 for 14nm, and 100 for 28nm, according to Gartner. My mental model of this process is completely wrong. I thought they'd have a Verilog code base, and moving to a new process was basically a recompile. What are they doing for 100/200/300/500 man-years, and why do the smaller processes take longer?
- williadc 11y agoYour mental model only covers the front-end of design. The back-end, where I work, is very dependant on process. You must update the design to take advantage of process improvements (otherwise why bother moving?), and the new process comes with new restrictions for placing transistors and interconnect that must be accounted for.
- petra 11y agoYour part of the process is a mystery relative to the front end - which is similar to fpga design. Can you explain/link to how your work process looks like ?
- vasco 11y agoIt means you live inside cadence actually drawing where metal will go, where poly will go and so on, you design the actual transistors, connections, everything. You do this design and you're constantly fixing warnings and errors about process limitations such as "this metal line can't be thinner than X amount", or "on level 3 you can't have this interconnect so closer together" and so on. Looks more or less like this: http://i.imgur.com/ECIVChO.png http://i.imgur.com/ECIVChO.png
- petra 11y agoThanks. But how does it Apply to a whole SOC ? you basically go to the critical sections and optimize them by hand, better than the synthesis tool ? Or just supply some basic components to the design team , and if so isn't it the job of the fab and the PDK(process design kit) ?
- mjrpes 11y agoCould anyone help me understand why is it 9 times more expensive to design a chip at 7nm than 28nm? I would have naively thought chip design is fairly automated, but a 9x increase makes is sound like every gate and path is delicately hand-stitched like a Persian rug.
- deegles 11y agoI think it's because at that point they can't use a single "mask" for the lithography and have to do multiple exposures with different masks. The equipment is also fabulously more expensive. The D1X site will have $6 billion invested: http://www.bizjournals.com/portland/news/2012/10/24/intel-plans-massive-expansion-to-3b.html http://www.bizjournals.com/portland/news/2012/10/24/intel-pl...
- mjrpes 11y agoI can understand the dramatically increased costs with chip production. But the article makes it sound like the 9x increase is with the design of the chip (e.g., with an HDL simulator).
- yaantc 11y agoThe design cost is increasing. It's not as in software where you write high level code (Verilog for IC) and let the compiler do its job, and in most cases you're done. For IC design, there's a two part process: the front-end design in Verilog, and then the back-end design to map this to the process implementation. With old nodes, the back-end was a simple affair and mostly automated --- software like. But with more advanced nodes it's no longer the case. The tools need proper constraints to generate something that will work (like timing constraints), and this need human input. And at the most advanced nodes, it's common that when you reach the back-end work one realize that the design is not good enough and need to be tweaked to let the tool generate a good implementation. This creates round-trips between back-end and Verilog level design. And these are slow and expensive round trips (synthesis, tests in the loop are heavy). So it's far from fully automatic. There's a lot of work done on the tools, but there are also a lot of additional constraints to deal with with each new nodes. It's a real complexity explosion, and this is what makes designs on advanced nodes so much more expensive. This a highly simplified description but hopefully enough to get a feeling for what's going on.
- wallacoloo 11y ago> TSMC is moving from a 2D layout scheme at 16nm to 1D technology at 10nm. 1D layouts are easier to make in the fab, but they involve more restrictive design rules. What is a 1D layout? Surely it must be something of a misnomer, as the only way I can visualize it is as a barcode, where each material you place has to span the entire width of the chip - and that seems utterly worthless.
- Panoramix 11y agoSome high end processes only allow you to pattern a bunch of parallel, narrow lines (hence 1D). These are subsequently "cut" in a useful way, and you can connect to them using a different layer above or below.
- abecedarius 11y ago> For a 10nm chip, it takes $120 million for the design cost, plus 60% for the embedded software. I don't understand: 60% of what? What embedded software?
- adapteva 11y agoPut simply "stuff". Take a look at Fred Brooks, mythical man month if you haven't ready it already. The projects that cost $250M will have over 1,000 engineers involved. Running a tightly coupled engineering project of that size is impossible in my opinion, thus the cost. Figure that 50% of the budget goes to communication overhead, 25% to management overhead, and you are left with 25% of true engineering costs.
- amirhirsch 11y ago"Moore's law is dead" is mostly false every time it's written. I would expect fixed costs to drop for 7nm so that more designs can go ASIC and benefit from lower cost per transistor and higher performance. Seems like even if we were locked at 7nm, decreasing NRE for custom SoCs will yield performance improvements for a long time coming.
- monocasa 11y agoI mean, that's like saying it's not really a car accident because even though the front of the car is crushing into the divider wall, the rear of the car is moving at almost the same speed.
- deleted 11y ago[deleted]
- freekh 11y agoI wonder if this will create create a market asics and FPGA when the lasts drops of perf has been squeezed out of the cpus (and GPU)?
- zanny 11y agoOnce we hit the wall of general CPU performance we will probably retrace a lot of old school custom hardware design. Expect a lot of the parts integrated into a CPU today to move back out, but simultaneously we will have to start shipping more sophisticated cooling solutions for denser CPU chips (since the main reason bridges were integrated were because dense cores were getting too hot for copper / aluminum fin heat transfer like most heatsinks). It will take a really long time to actually squeeze out CPU optimization. We are still contending with most software not even properly scaling to four cores, let alone well implemented job queue systems for arbitrarily scaled cores. And once the chips start dropping in price as the node standardizes and companies can lay off the intense R&D investments, we can start introducing more heterogeneous compute clusters to drive performance cheaper even when the silicon itself is stuck until graphene takes the market.
- Lind5 11y agoPain Points at 7nm also an interesting read http://semiengineering.com/pain-points-at-7nm/ http://semiengineering.com/pain-points-at-7nm/
- cft 11y agoOne interesting consequence is that this will probably impose a ceiling on Google's growth.
- Animats 11y agoSmaller line size doesn't mean more compute power any more. Clocks maxed out around 3GHz some years ago. For CPUs, getting rid of the heat has become the limiting factor. (Yes, with aggressive cooling you can go faster, but most systems don't go there.) Electromigration is starting to limit component lifespans. But that's for CPUs. Memory, especially mostly-inactive memory such as flash devices, still has a few iterations ahead. Memory devices can tolerate and recover from bad cells and bad rows. There's also the option of going 3D and stacking memory. That doesn't work for CPUs because getting the heat out of the middle is very tough. The other big problem is cost. Fabs have become multi-billion dollar projects. The article says that designing an SOIC for 7mm costs upwards of $200 million. (Why? Design tools? Mask making?) If cost per gate declines, we can still get more compute power by making bigger parts with more CPUs. Single CPU performance probably isn't going to climb much more, though. Fortunately, most of the things we want to do in machine learning and AI can be done in parallel. This problem isn't going to keep us from getting to AI.
- martinald 11y agoI think people are really underestimating how poor CPU performance improvement has been recently; it's been totally masked by I/O (SSD) and RAM improvements. Before SSD it was common to see a CPU wasting >50% of its time waiting for IO. Now you rarely see iowait being a problem.
- dc2 11y agoAnyone else getting a 404?
- nuand 11y agoYea, I am too