3 ms·

This should be a good read. I aspired to do stuff like this in my undergrad: https://github.com/nickdesaulniers/Omicron/blob/master/ProjectReport.pdf https://g

This should be a good read. I aspired to do stuff like this in my undergrad: https://github.com/nickdesaulniers/Omicron/blob/master/ProjectReport.pdf https://github.com/nickdesaulniers/Omicron/blob/master/Proje... People like the author, Andrew Waterman, and others like Bunnie Huang who work towards making more of computing open are inspiring. I feel like the last piece of the puzzle is open FPGAs. I'm quite sure FPGAs are critical to the open hardware movement. I should quit Google and solve this...

ndesaulniers 11y ago
Also, some choice quotes I've pulled while reading chpt2 ("Why Develop a New Instruction Set?"): * MIPS: ...MIPS remains a trademark of Imagination Technologies; MIPS compatibility cannot be claimed without their permission. * SPARC: SPARC Intl. continues to grant licenses for v8 and v9...for $99...[but] continued development of Oracle SPARC is proprietary. * Alpha: The Alpha also highlights an important risk of using commercial ISAs: they can die. * ARMv7: Between ARM[v7] and THUMB, there are over 600 instructions...NEON adds hundreds more. * ARMv8: The compact THUMB instruction set has not been brought along to the 64-bit address space...as we show in cpht5, it cannot compete in code size with a variable length ISA. * 80x86: Intel [has done all these great things]...the design quality of the ISA is not one of them.
- nickpsecurity 11y ago
  Good list. Let me add to it. SPARC: Don't forget the only production-ready, GPL'd CPU from Gaisler & its proprietary improvements. Also, Fujitsu and Russia have SPARC processors. Not just Oracle. Fujitsu's are badass. http://www.gaisler.com/index.php/products/processors/leon3 http://www.gaisler.com/index.php/products/processors/leon3 http://www.gaisler.com/index.php/products/processors/leon4?task=view&id=338 http://www.gaisler.com/index.php/products/processors/leon4?t... Alpha: Yes, it died. However, my digging found that Intel and Samsung spun it off into a dedicated company licensing Alpha to anyone interested. Only found one vendor that bought it for machines. Nobody major wanted it to exist enough to buy a license. So, the market killed it. ARM: Similar issues to MIPS in that ARM will sue your ass any chance they get. There's a reason the clone went with ARMv2 and said it was not for profit. ;) Intel did a great one in the past. Still available but crippled. Look here: https://en.wikipedia.org/wiki/Intel_i960 https://en.wikipedia.org/wiki/Intel_i960 POWER and PPC stayed head to head with Intel for years with many PPC cores and boards in embedded. Even in FPGA's. They also accelerated decimal ops nice for business apps. https://en.wikipedia.org/wiki/PowerPC https://en.wikipedia.org/wiki/PowerPC Dreamcast had a Super-H. Those are still around with their own cost-benefit analysis: https://en.wikipedia.org/wiki/SuperH https://en.wikipedia.org/wiki/SuperH
  - smcl 11y ago
    Just to add a little bit more - there's been a handful of developments around the SuperH as patents start to lapse. The Open Processor Foundation have a couple of SuperH implementations you can use on an FPGA (note: I haven't tried this) they've got a bit of information up at their website: http://0pf.org/ http://0pf.org/ However this article is a better introduction IMO: https://lwn.net/Articles/647636/ https://lwn.net/Articles/647636/
    - nickpsecurity 11y ago
      Yep. Neat that it's getting a revival.
  - protomyth 11y ago
    I never had a chance to play with the i960, what made it great? I seriously wish the SH-5 had actually been released and the new POWER chips were actually available in a bit of a cheaper form.
    - nickpsecurity 11y ago
      True on PPC and SH5. Far as i960, you need to know the context. Look at these: https://en.m.wikipedia.org/wiki/Intel_iAPX_432 https://en.m.wikipedia.org/wiki/Intel_iAPX_432 https://en.m.wikipedia.org/wiki/BiiN https://en.m.wikipedia.org/wiki/BiiN https://en.m.wikipedia.org/wiki/Intel_i960 https://en.m.wikipedia.org/wiki/Intel_i960 The i432 was their most original work. It was a mainframe, capability-addressed, error recovery, and OS/apps in safe Ada. Did too much in hardware, though. BiiN had i960 which kept best parts of that. Think fast RISC with high reliability and security features.
  - KMag 11y ago
    I'm curious why there wasn't more interest in the DEC Alpha AXP. It was designed from the beginning as a 64-bit chip (unlike x86, POWER, ARM, MIPS, HP PA-RISC, and almost everything else except Itanium). It consciously avoided features (and memory model features) that interfered with efficient parallel superscalar implementations. The Ultrix, Linux, and VMS kernels didn't run in privileged mode, but instead made upcalls into PAL code (a kind of super lightweight hypervisor). Any insights as to why the Alpha AXP didn't get more interest after it was dropped by DEC / HP?
- carussell 11y ago
  > SPARC Intl. continues to grant licenses for v8 and v9...for $99...[but] continued development of Oracle SPARC is proprietary. Can anyone explain this situation? There are multiple freely licensed (GPL or LGPL) SPARC IP cores, but SPARC is still described as proprietary?
heathjohns 11y ago
It's going to be a very interesting space, IMO. The thing about FPGAs is that they are deeply dependant on storage technology. Right now their gate configuration is kept in SRAM loaded in at boot, which is the worst of all worlds. Not only is it non-volatile, it's very power hungry and takes up more than half of the space on the chip. And flash memory hasn't helped much because (from what I've been able to figure out) having tiny sections of flash for each logic element is impractical due to the physics of how it works. However, flash and SRAM aren't the end of the line, and advances in non-volatile memory will disproportionately affect FGPAs. It seems almost inevitable to me that the NVM landscape will be changing soon: several technologies are being worked on in parallel (e.g. NRAM and RRAM) - one of them is going to win, there's just too much demand for higher performance storage. When that happens, FPGAs will get to draft behind the huge tech investment made for the sake of SSDs etc. FPGAs with tiny NVM will look a lot more like structured ASICs (a prefabbed grid of gates, with a custom metal interconnect layer) than their current form. Instead of needing ~10x power and supporting ~1/4 the clock speeds, it'd be about half as fast and twice the power - still not ideal, but within spitting distance of the advantages of FPGAs outweighing the disadvantages vs. ASICs, and certainly a qualitative difference from where we're at today. This, combined with having the same thoughts as you about the criticalness to open computing, has gotten me to start working on improving the tooling for people just getting into FPGAs. It's hard to have an openness-based movement when there's not enough people, and it's hard to get people in if the first rung of the ladder's too high (e.g. installing a grab-bag of software and learning Verilog as step #1). Here's my (very alpha) work so far: http://blinklight.io http://blinklight.io (I haven't publicized it yet because I'm going to be doing a big change to the pitch/target market soon). I'm well aware of the limitations of visual programming, but I think it's an excellent basis for developing intuition before moving on to HDLs (especially for people coming from software who are thrown off by Verilog's superficial similarities to C).

ndesaulniers 11y ago

Also, some choice quotes I've pulled while reading chpt2 ("Why Develop a New Instruction Set?"): * MIPS: ...MIPS remains a trademark of Imagination Technologies; MIPS compatibility cannot be claimed without their permission. * SPARC: SPARC Intl. continues to grant licenses for v8 and v9...for $99...[but] continued development of Oracle SPARC is proprietary. * Alpha: The Alpha also highlights an important risk of using commercial ISAs: they can die. * ARMv7: Between ARM[v7] and THUMB, there are over 600 instructions...NEON adds hundreds more. * ARMv8: The compact THUMB instruction set has not been brought along to the 64-bit address space...as we show in cpht5, it cannot compete in code size with a variable length ISA. * 80x86: Intel [has done all these great things]...the design quality of the ISA is not one of them.

nickpsecurity 11y ago
Good list. Let me add to it. SPARC: Don't forget the only production-ready, GPL'd CPU from Gaisler & its proprietary improvements. Also, Fujitsu and Russia have SPARC processors. Not just Oracle. Fujitsu's are badass. http://www.gaisler.com/index.php/products/processors/leon3 http://www.gaisler.com/index.php/products/processors/leon3 http://www.gaisler.com/index.php/products/processors/leon4?task=view&id=338 http://www.gaisler.com/index.php/products/processors/leon4?t... Alpha: Yes, it died. However, my digging found that Intel and Samsung spun it off into a dedicated company licensing Alpha to anyone interested. Only found one vendor that bought it for machines. Nobody major wanted it to exist enough to buy a license. So, the market killed it. ARM: Similar issues to MIPS in that ARM will sue your ass any chance they get. There's a reason the clone went with ARMv2 and said it was not for profit. ;) Intel did a great one in the past. Still available but crippled. Look here: https://en.wikipedia.org/wiki/Intel_i960 https://en.wikipedia.org/wiki/Intel_i960 POWER and PPC stayed head to head with Intel for years with many PPC cores and boards in embedded. Even in FPGA's. They also accelerated decimal ops nice for business apps. https://en.wikipedia.org/wiki/PowerPC https://en.wikipedia.org/wiki/PowerPC Dreamcast had a Super-H. Those are still around with their own cost-benefit analysis: https://en.wikipedia.org/wiki/SuperH https://en.wikipedia.org/wiki/SuperH
- smcl 11y ago
  Just to add a little bit more - there's been a handful of developments around the SuperH as patents start to lapse. The Open Processor Foundation have a couple of SuperH implementations you can use on an FPGA (note: I haven't tried this) they've got a bit of information up at their website: http://0pf.org/ http://0pf.org/ However this article is a better introduction IMO: https://lwn.net/Articles/647636/ https://lwn.net/Articles/647636/
  - nickpsecurity 11y ago
    Yep. Neat that it's getting a revival.
- protomyth 11y ago
  I never had a chance to play with the i960, what made it great? I seriously wish the SH-5 had actually been released and the new POWER chips were actually available in a bit of a cheaper form.
  - nickpsecurity 11y ago
    True on PPC and SH5. Far as i960, you need to know the context. Look at these: https://en.m.wikipedia.org/wiki/Intel_iAPX_432 https://en.m.wikipedia.org/wiki/Intel_iAPX_432 https://en.m.wikipedia.org/wiki/BiiN https://en.m.wikipedia.org/wiki/BiiN https://en.m.wikipedia.org/wiki/Intel_i960 https://en.m.wikipedia.org/wiki/Intel_i960 The i432 was their most original work. It was a mainframe, capability-addressed, error recovery, and OS/apps in safe Ada. Did too much in hardware, though. BiiN had i960 which kept best parts of that. Think fast RISC with high reliability and security features.
- KMag 11y ago
  I'm curious why there wasn't more interest in the DEC Alpha AXP. It was designed from the beginning as a 64-bit chip (unlike x86, POWER, ARM, MIPS, HP PA-RISC, and almost everything else except Itanium). It consciously avoided features (and memory model features) that interfered with efficient parallel superscalar implementations. The Ultrix, Linux, and VMS kernels didn't run in privileged mode, but instead made upcalls into PAL code (a kind of super lightweight hypervisor). Any insights as to why the Alpha AXP didn't get more interest after it was dropped by DEC / HP?
carussell 11y ago
> SPARC Intl. continues to grant licenses for v8 and v9...for $99...[but] continued development of Oracle SPARC is proprietary. Can anyone explain this situation? There are multiple freely licensed (GPL or LGPL) SPARC IP cores, but SPARC is still described as proprietary?

heathjohns 11y ago

It's going to be a very interesting space, IMO. The thing about FPGAs is that they are deeply dependant on storage technology. Right now their gate configuration is kept in SRAM loaded in at boot, which is the worst of all worlds. Not only is it non-volatile, it's very power hungry and takes up more than half of the space on the chip. And flash memory hasn't helped much because (from what I've been able to figure out) having tiny sections of flash for each logic element is impractical due to the physics of how it works. However, flash and SRAM aren't the end of the line, and advances in non-volatile memory will disproportionately affect FGPAs. It seems almost inevitable to me that the NVM landscape will be changing soon: several technologies are being worked on in parallel (e.g. NRAM and RRAM) - one of them is going to win, there's just too much demand for higher performance storage. When that happens, FPGAs will get to draft behind the huge tech investment made for the sake of SSDs etc. FPGAs with tiny NVM will look a lot more like structured ASICs (a prefabbed grid of gates, with a custom metal interconnect layer) than their current form. Instead of needing ~10x power and supporting ~1/4 the clock speeds, it'd be about half as fast and twice the power - still not ideal, but within spitting distance of the advantages of FPGAs outweighing the disadvantages vs. ASICs, and certainly a qualitative difference from where we're at today. This, combined with having the same thoughts as you about the criticalness to open computing, has gotten me to start working on improving the tooling for people just getting into FPGAs. It's hard to have an openness-based movement when there's not enough people, and it's hard to get people in if the first rung of the ladder's too high (e.g. installing a grab-bag of software and learning Verilog as step #1). Here's my (very alpha) work so far: http://blinklight.io http://blinklight.io (I haven't publicized it yet because I'm going to be doing a big change to the pitch/target market soon). I'm well aware of the limitations of visual programming, but I think it's an excellent basis for developing intuition before moving on to HDLs (especially for people coming from software who are thrown off by Verilog's superficial similarities to C).