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Isn't NUMA how multi-core CPUs work still? At least the AMD Bulldozer architecture diagram on the Wikipedia NUMA page shows this, both within a socket and betw

Isn't NUMA how multi-core CPUs work still? At least the AMD Bulldozer architecture diagram on the Wikipedia NUMA page shows this, both within a socket and between sockets: https://en.wikipedia.org/wiki/Non-uniform_memory_access#/media/File:Hwloc.png https://en.wikipedia.org/wiki/Non-uniform_memory_access#/med... Is the same true for Intel chips? (The Wikipedia page mentions the Intel E8870 memory controller, but not whether newer chips use similar set-ups)

feld 10y ago
To my understanding, multi core on a single package (CPU) is much simpler to schedule. There are performance penalties if you schedule work on a package that has to access memory that is not directly connected. A NUMA-aware scheduler should not make this mistake.
signa11 10y ago
> Isn't NUMA how multi-core CPUs work still? if you have > 1 socket, then yes, otherwise no. Edit: added verb
- wyldfire 10y ago
  These days, yeah, that's definitely the case. A few generations back there were a couple of multi-socket-single-memory-domain designs.
  - voidlogic 10y ago
    > A few generations back there were a couple of multi-socket-single-memory-domain designs. Core2Quad/Duo based Xeons, P4s, Athlon MP, etc
    - vonmoltke 10y ago
      I thought the Core2 chips were actually multiple single-core processors on a single slab, which would make that true of all Core2 machines (not just Xeons). I was pretty deep in Nehalem details when it first came out and was under the impression that microarchitecture was Intel's first true multi-core chip (as in, the cores were actually integrated on the die). Could be wrong, though, since I never delved into the Core2 architecture.
      - voidlogic 10y ago
        >I thought the Core2 chips were actually multiple single-core processors on a single slab, which would make that true of all Core2 machines (not just Xeons) Correct.
qaq 10y ago
Looks like you are right Intel QuickPath Interconnect is similar to what AMD was doing with HT.

feld 10y ago

To my understanding, multi core on a single package (CPU) is much simpler to schedule. There are performance penalties if you schedule work on a package that has to access memory that is not directly connected. A NUMA-aware scheduler should not make this mistake.

signa11 10y ago

> Isn't NUMA how multi-core CPUs work still? if you have > 1 socket, then yes, otherwise no. Edit: added verb

wyldfire 10y ago
These days, yeah, that's definitely the case. A few generations back there were a couple of multi-socket-single-memory-domain designs.
- voidlogic 10y ago
  > A few generations back there were a couple of multi-socket-single-memory-domain designs. Core2Quad/Duo based Xeons, P4s, Athlon MP, etc
  - vonmoltke 10y ago
    I thought the Core2 chips were actually multiple single-core processors on a single slab, which would make that true of all Core2 machines (not just Xeons). I was pretty deep in Nehalem details when it first came out and was under the impression that microarchitecture was Intel's first true multi-core chip (as in, the cores were actually integrated on the die). Could be wrong, though, since I never delved into the Core2 architecture.
    - voidlogic 10y ago
      >I thought the Core2 chips were actually multiple single-core processors on a single slab, which would make that true of all Core2 machines (not just Xeons) Correct.

qaq 10y ago

Looks like you are right Intel QuickPath Interconnect is similar to what AMD was doing with HT.