For example Skylake technically has 4 FPU's per physical core 1 SIMD, 3 x87 FPU-esque units, 1 branch processors, and 3-4ish IPU's (branch processors have some

For example Skylake technically has 4 FPU's per physical core 1 SIMD, 3 x87 FPU-esque units, 1 branch processors, and 3-4ish IPU's (branch processors have some IPU uOPs)? Maybe I'm misunderstanding, but that's a very odd description of the execution units in a Skylake core. It might be better to say: "Skylake can sustain execution of 4 instructions per cycle, up to three of which can perform 256-bit vector operations." Section 2.1 here gives an exact diagram: http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf http://www.intel.com/content/dam/www/public/us/en/documents/...