I would think it would be difficult to achieve the low jitter of a simple, fixed # of cycles / instruction, architecture like AVR in a superscalar, cached, spec

I would think it would be difficult to achieve the low jitter of a simple, fixed # of cycles / instruction, architecture like AVR in a superscalar, cached, speculative architecture like modern X86 CPUs. A hard RTOS is necessary, but perhaps not sufficient with most X86 microarchs. Maybe you can disable some of that dynamic behavior via MSRs but probably not all.