I don't have direct knowledge of current yield rates, so this is speculation. That said, I did give what I think is a reasonable order of magnitude in the abov

I don't have direct knowledge of current yield rates, so this is speculation. That said, I did give what I think is a reasonable order of magnitude in the above comment when I said a company would have trouble affording a rate of 1 in a billion transistors for unclustered defects. I meant that literally. Some chips just probably can't be profitable with a rate that high. Nvidia might be able to make yield on that rate since GPUs have enough functional duplication, but I'd expect Intel's rate to be under one in a billion and over one in a trillion. Also note that clustered failures are different. Some whole wafers might be junk if alignment is off, or if there's a bubble somewhere, a series of adjacent chips would be destroyed. If you throw a whole wafer away, that thankfully doesn't mean you have to produce a billion perfect wafers to make up for it. So the yield rate above would only need to apply for the parts where the process is otherwise dialed in. If you have a bubble or alignment issue, it really doesn't matter at that point whether you kill tens of transistors or a few billion, any chips where the bubble is are likely just gonna get marked and tossed. And it is sometimes routine on some types of lines that if the chip yield is low enough on a wafer the whole thing is tossed since it's not economical to cut and further test and package up any working ones. Semiconductor economics are pretty nuts. It's actually more common to specify error rate in terms of defects per mm^2, because the exact number of transistors involved in the defect is mostly irrelevant if it's a defect that is wide ranging.