4 ms·
You might be surprised to learn that AVX-512 is not available in Skylake - it will only be in the Xeon line. It also won't give you anywhere near double perform
by eloff 11y ago
You might be surprised to learn that AVX-512 is not available in Skylake - it will only be in the Xeon line. It also won't give you anywhere near double performance, since a lot of AVX2 code is memory bandwidth bound anyway (which is probably one of the reasons it's not in the desktop chips.) I would've bought a Skylake so that I can test code on an AV-512 machine. Now I'll keep my money and wait and see.
- vardump 11y agoCurrent Skylake Xeons don't have AVX-512 either. For example no AVX-512 in this Skylake Xeon: http://ark.intel.com/products/93354/Intel-Xeon-Processor-E3-1575M-v5-8M-Cache-3_00-GHz http://ark.intel.com/products/93354/Intel-Xeon-Processor-E3-... I know about bandwidth issues, but you can also use big vector sizes to mitigate, more opportunities for simple schemes for realtime (de)compression of data. (Usually called packing/unpacking). But where you can work around bandwidth issues, you can get up to twice as much work done. I've also been looking for such a chip to test my code. Of course it's possible to use SDE. https://software.intel.com/en-us/articles/intel-software-development-emulator https://software.intel.com/en-us/articles/intel-software-dev...
- eloff 11y agoYeah the E3 Xeons won't have it, they're basically desktop chips dressed up. The E5s are supposed to have it though.