3 ms·

I don't know about other people, but my next Intel CPU will have AVX-512, which Skylake doesn't have. I'm expecting AVX-512 to (up to) double integer/FPU vector

by vardump 11y ago

I don't know about other people, but my next Intel CPU will have AVX-512, which Skylake doesn't have. I'm expecting AVX-512 to (up to) double integer/FPU vector computation capacity. I also want to see some proof future Intel processors (especially 10nm and smaller) have not lost durability due to electromigration [1] (or some other durability issues small feature size can cause). There's already some indication this might be happening on current Skylake CPUs. Of course not all workloads will get faster, but it could help with things like parsing (XML, json, etc.), games, media processing, compression, physics simulation, etc. -- or really anything vectorizable that needs to run on CPU for reason or another. [1]: https://en.wikipedia.org/wiki/Electromigration https://en.wikipedia.org/wiki/Electromigration

eloff 11y ago
You might be surprised to learn that AVX-512 is not available in Skylake - it will only be in the Xeon line. It also won't give you anywhere near double performance, since a lot of AVX2 code is memory bandwidth bound anyway (which is probably one of the reasons it's not in the desktop chips.) I would've bought a Skylake so that I can test code on an AV-512 machine. Now I'll keep my money and wait and see.
- vardump 11y ago
  Current Skylake Xeons don't have AVX-512 either. For example no AVX-512 in this Skylake Xeon: http://ark.intel.com/products/93354/Intel-Xeon-Processor-E3-1575M-v5-8M-Cache-3_00-GHz http://ark.intel.com/products/93354/Intel-Xeon-Processor-E3-... I know about bandwidth issues, but you can also use big vector sizes to mitigate, more opportunities for simple schemes for realtime (de)compression of data. (Usually called packing/unpacking). But where you can work around bandwidth issues, you can get up to twice as much work done. I've also been looking for such a chip to test my code. Of course it's possible to use SDE. https://software.intel.com/en-us/articles/intel-software-development-emulator https://software.intel.com/en-us/articles/intel-software-dev...
  - eloff 11y ago
    Yeah the E3 Xeons won't have it, they're basically desktop chips dressed up. The E5s are supposed to have it though.

by vardump 11y ago

eloff 11y ago

You might be surprised to learn that AVX-512 is not available in Skylake - it will only be in the Xeon line. It also won't give you anywhere near double performance, since a lot of AVX2 code is memory bandwidth bound anyway (which is probably one of the reasons it's not in the desktop chips.) I would've bought a Skylake so that I can test code on an AV-512 machine. Now I'll keep my money and wait and see.

vardump 11y ago
Current Skylake Xeons don't have AVX-512 either. For example no AVX-512 in this Skylake Xeon: http://ark.intel.com/products/93354/Intel-Xeon-Processor-E3-1575M-v5-8M-Cache-3_00-GHz http://ark.intel.com/products/93354/Intel-Xeon-Processor-E3-... I know about bandwidth issues, but you can also use big vector sizes to mitigate, more opportunities for simple schemes for realtime (de)compression of data. (Usually called packing/unpacking). But where you can work around bandwidth issues, you can get up to twice as much work done. I've also been looking for such a chip to test my code. Of course it's possible to use SDE. https://software.intel.com/en-us/articles/intel-software-development-emulator https://software.intel.com/en-us/articles/intel-software-dev...
- eloff 11y ago
  Yeah the E3 Xeons won't have it, they're basically desktop chips dressed up. The E5s are supposed to have it though.