> 32 FP ops per clock? I don't think that is true, and if it is it is very misleading. https://www.google.com/search?q=haswell+32+single+precision+floating+poi

> 32 FP ops per clock? I don't think that is true, and if it is it is very misleading. https://www.google.com/search?q=haswell+32+single+precision+floating+point+operations+per+cycle https://www.google.com/search?q=haswell+32+single+precision+... > First with Haswell introducing the fused multiply add, suddenly all the 'peak flops' numbers doubled, which is technically true, but only if everything you do is a fused multiply add (with no cache misses of course). Yeah, FMA (fused multiply-adds). Better or worse, it's de facto standard to quote one FMA as two FLOPS, because it's a very commonly combined operation. > Are you saying that AVX instructions are pipelined (or some other technique) and have a throughput greater than their width per cycle? Yeah, AFAIK, they're (mostly) pipelined and dual issue per clock.