Correct; the CPU and the end-point accelerator both must cooperate to negotiate the CAPI link. Disclaimer: I work on this with some very smart people @ IBM. Op

Correct; the CPU and the end-point accelerator both must cooperate to negotiate the CAPI link. Disclaimer: I work on this with some very smart people @ IBM. Opinions are my own. When a PCIe device is in CAPI mode, the PCIe protocol is used as a transport layer, but the CAPI protocol rides on top, and hardware in the CPU's PHB (the CAPP unit) and hardware in the accelerator (the PSL in this case) cooperate to present the common address space to the process and to the accelerator itself. [1] If a CAPI-capable card's plugged in to a non-CAPI-capable slot, it remains a PCI card. If a non-CAPI card's plugged in to a CAPI-capable system, it remains a PCI card. If both sides match on protocol versions and the kernel contains the cxl driver, the kernel will switch the slot into CAPI mode, and the CAPP unit and PSL effectively take over the PCI link on either side. [1] http://events.linuxfoundation.org/sites/events/files/slides/lcjp15_mackerras.pdf http://events.linuxfoundation.org/sites/events/files/slides/... - see page 13+ for some GPU / NVLink materials, and page 24+ for CAPI materials (oh - and I worked on the product who's data is quoted on page 29 [2]! [2] https://www.ibm.com/developerworks/community/blogs/fe313521-2e95-46f2-817d-44a4f27eba32/entry/power8_capi_flash_in_memory_expansion_to_speed_data_access?lang=en https://www.ibm.com/developerworks/community/blogs/fe313521-...