Try interfacing one of them with DRAM, at a moderate speed. You'll learn: Pipelines, Caches, Why cache misses are so painful and a whole host of CPU performanc

Try interfacing one of them with DRAM, at a moderate speed. You'll learn: Pipelines, Caches, Why cache misses are so painful and a whole host of CPU performance stuff that "looks" esoteric will become plain as day.