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Have you tried Vivado? Xilinx ISE is hands down terrible, but supposedly Vivado was "500 man-years of engineering effort" [1]. Unfortunately, vendor lock-in me
by Cieplak 11y ago
Have you tried Vivado? Xilinx ISE is hands down terrible, but supposedly Vivado was "500 man-years of engineering effort" [1]. Unfortunately, vendor lock-in means I can't try Altera's tools for my boards, but Vivado's high level synthesis is really cool. It generates a hardware design from a given C program, and then let's you tune the generated verilog [2].
[1]: http://www.eejournal.com/archives/articles/20120501-bigdeal http://www.eejournal.com/archives/articles/20120501-bigdeal
[2]: http://xillybus.com/tutorials/vivado-hls-c-fpga-howto-1 http://xillybus.com/tutorials/vivado-hls-c-fpga-howto-1
- JamilD 11y agoVivado is miles ahead of Quartus, especially for beginners. Altera's tools have a very steep learning curve for beginners to hardware.
- deleted 11y ago[deleted]
- blackguardx 11y agoI think that is mainly a matter of opinion. Unfortunately, you can't use Vivado with Xilinx's older, cheaper chips. I think beginners are more likely to use these chips than their more advanced, expensive chips. We'll have to see if the Spartan-7 is supported by Vivado or not.
- asb 11y agoThe newish Arty board has a 7-series part and is only $99
- blackguardx 11y agoI've been wanting to try it, but for some reason Xilinx refuses to offer support for the Spartan-6. They only offer support for their expensive chips.
- ShinyCyril 11y agoI haven't checked out the high-level synthesis part, but I've been using Vivado for a project recently and it's absolutely horrible. To name some of the issues I've had; - Memory leaks (grows from about 1GB to 11GB and starts swapping in a couple of minutes when editing existing IP) - Single-threaded synthesis is slow (though isn't limited to Vivado specifically) - Failing after 20 minutes of synthesis because of errors that would be easy to check at the start - Placing debug cores can result in needing to synthesise, find something went wrong, delete debug core, re-synthesise, re-add debug nets, synthesise again... - Aggressive caching results in it trying to find nets which were changed and no longer exist, despite re-creating the IP in question from scratch - Vivado creates a ridiculous amount of temporary files and is a royal pain to use with version control (there is an entire document which details the methods to use if you want to create a project to be stored under version control) I've been playing around with IceStorm for the iCE40 device and it's an absolute joy to use: fast, stable and simple. I appreciate that there are a lot of complex tools and reports which Vivado provides, but I would much rather use an open source tool like IceStorm for synthesis alongside the advanced tools from Vivado.