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No it doesn't. It translates the verilog source into C which it compiles to a native executable for simulation.
by zik 11y ago
No it doesn't. It translates the verilog source into C which it compiles to a native executable for simulation.
- buserror 11y agoOn a related note, ghdl [0] is a similar project but for VHDL. I spent a lot of time using it before I switched to verilog, it's a pretty nice tool on the other side of the fence. [0]: http://home.gna.org/ghdl/ http://home.gna.org/ghdl/