3 ms·
The straw man is the part I quoted. He talked about slow operations that gate your chip. Pipelining explicitly address this. Unless their async units have bett
by vvanders 11y ago
The straw man is the part I quoted.
He talked about slow operations that gate your chip. Pipelining explicitly address this. Unless their async units have better hold times than d-flops they will both be gated by propagation delay. It's a straw man since it never mentions pipelining at all.
[edit]Not that I don't have a ton of respect for Sutherland(esp in graphics domain) but it would be nice to see something that admits other approaches.
- Taniwha 11y agonot quite - pipe stages have costs - both in area and flop delay. In particular a particular flip-flop might have a setup time on it's input and a clk->Q delay - for really fast clocks this might be close to 1/4 your clock period. For example let's suppose we have a combined flop delay of 1nS and we have a combinatorial delay (the logic we want to calculate) of 9nS - we can clock this at 100MHz, or we can pipeline it 3 ways split the combinatorial block into 3 3nS chunks - each pipe stage still has a 1nS flop delay so total pipe stage delay is 4nS (250MHz) - we split the logic in 3 but only got a 2.5 times performance increase because of fixed costs Pipelining is a great tool but there is a law of diminishing returns that kicks in here
- vvanders 11y agoThanks, this is the kind of reply I was hoping to get instead of being told I can't comment because some has an important last name.
- CyberDildonics 11y agoI never said that, don't turn yourself into a victim.
- CyberDildonics 11y agoBut you didn't quote anything