5 ms·

I agree that LEON is overlooked in the MCU market. Wrapping up one or multiple of the RISC-V cores in GRLIB is something I think would benefit both Gaisler and

I agree that LEON is overlooked in the MCU market. Wrapping up one or multiple of the RISC-V cores in GRLIB is something I think would benefit both Gaisler and the RISC-V community and something I have thought of doing myself if I had the time!

nickpsecurity 11y ago
That's about half the peer review I need on that given your background. Next I need a SPARC opponent with HW/SOC experience background giving same recommend haha. Might send it to some of the academics. Another part of my plan was to get academics to build and public domain the source/verilog/whatever so we can benefit from their cheap EDA licensing and shuttle runs. Pick bare minimum I.P. we need, like DDR or PCI, to get SOC's working. Slowly crank them out at many universities to eventually arrive at a platform with ASIC-proven components. Then, startups can just do integrations with whatever little part is custom for them. Much cheaper. Also, I think analog academics doing open, cell libraries would be a good idea at 350, 180, 90, 45, and 28nm. As money comes in, can just shrink from one tech to another using pre-existing I.P. or cells. People could probably use Qflow OSS ASIC flow with 350nm (maybe 180nm) without or w/ little commercial tooling. Always looking for HW people's review on these things. What you think?
- kristoffer 11y ago
  Academics should absolutely open source their stuff to a larger degree and contribute it a common open source community. I don't think LEON/GRLIB will be that community but may be a part of it. OpenCores did not succeed but I have hopes for what's cooking around FOSSi foundation/LibreCores.
- analognoise 11y ago
  Most academic shuttle runs are still at 90nm, or bigger. There are a few reasons for this: cost of runs, cost of tooling (hundreds of k), and the fact that your assumptions about transistor action and modeling are exponentially more complicated at advanced process nodes. Academics also sign NDAs about the processes they use, and can only make certain things available; the most open is probably MOSIS, but that's absolutely no good for advanced nodes. I'd say throw low power and advanced anything out the window, demonstrate a working chip, then look for funding to advance it.
  - nickpsecurity 11y ago
    I'd agree that most runs are at 90nm or above. Yet, the rest is confusing given I have quite a few papers with competitive stuff done at 45-65nm with some at 28 or 32nm. So, why you say forget about it or MOSIS below 90nm if academics are getting working chips done that low?
    - analognoise 11y ago
      They sign NDAs for the process and get 100-thousand dollar layout packages for academic prices. If you have a few spare million dollars, you still can't necessarily release a lot of data due to the NDAs - usually they give you models for the processes that are proprietary (and they invested a lot in developing, and so will consider any breach an act of war).
      - LargoLasskhyfv 11y ago
        From my amateurish POV this looks rather peacefully. No Cult of the NDA in sight. Nonetheless too expensive. OTOH, are you aware of the prices mentioned there? http://www.europractice-ic.com/ http://www.europractice-ic.com/ http://www.europractice.stfc.ac.uk/welcome.html http://www.europractice.stfc.ac.uk/welcome.html http://cmp.imag.fr/ http://cmp.imag.fr/ http://cmp.imag.fr/products/ic/?p=prices2014 http://cmp.imag.fr/products/ic/?p=prices2014 http://cmp.imag.fr/products/ic/?p=prices2015 http://cmp.imag.fr/products/ic/?p=prices2015 http://cmp.imag.fr/products/ic/?p=prices2016 http://cmp.imag.fr/products/ic/?p=prices2016 ahh crap..."which are sent to customers upon signature of a Confidentiality and License Agreement" anyways, prices...hope that helps

nickpsecurity 11y ago

That's about half the peer review I need on that given your background. Next I need a SPARC opponent with HW/SOC experience background giving same recommend haha. Might send it to some of the academics. Another part of my plan was to get academics to build and public domain the source/verilog/whatever so we can benefit from their cheap EDA licensing and shuttle runs. Pick bare minimum I.P. we need, like DDR or PCI, to get SOC's working. Slowly crank them out at many universities to eventually arrive at a platform with ASIC-proven components. Then, startups can just do integrations with whatever little part is custom for them. Much cheaper. Also, I think analog academics doing open, cell libraries would be a good idea at 350, 180, 90, 45, and 28nm. As money comes in, can just shrink from one tech to another using pre-existing I.P. or cells. People could probably use Qflow OSS ASIC flow with 350nm (maybe 180nm) without or w/ little commercial tooling. Always looking for HW people's review on these things. What you think?

kristoffer 11y ago
Academics should absolutely open source their stuff to a larger degree and contribute it a common open source community. I don't think LEON/GRLIB will be that community but may be a part of it. OpenCores did not succeed but I have hopes for what's cooking around FOSSi foundation/LibreCores.
analognoise 11y ago
Most academic shuttle runs are still at 90nm, or bigger. There are a few reasons for this: cost of runs, cost of tooling (hundreds of k), and the fact that your assumptions about transistor action and modeling are exponentially more complicated at advanced process nodes. Academics also sign NDAs about the processes they use, and can only make certain things available; the most open is probably MOSIS, but that's absolutely no good for advanced nodes. I'd say throw low power and advanced anything out the window, demonstrate a working chip, then look for funding to advance it.
- nickpsecurity 11y ago
  I'd agree that most runs are at 90nm or above. Yet, the rest is confusing given I have quite a few papers with competitive stuff done at 45-65nm with some at 28 or 32nm. So, why you say forget about it or MOSIS below 90nm if academics are getting working chips done that low?
  - analognoise 11y ago
    They sign NDAs for the process and get 100-thousand dollar layout packages for academic prices. If you have a few spare million dollars, you still can't necessarily release a lot of data due to the NDAs - usually they give you models for the processes that are proprietary (and they invested a lot in developing, and so will consider any breach an act of war).
    - LargoLasskhyfv 11y ago
      From my amateurish POV this looks rather peacefully. No Cult of the NDA in sight. Nonetheless too expensive. OTOH, are you aware of the prices mentioned there? http://www.europractice-ic.com/ http://www.europractice-ic.com/ http://www.europractice.stfc.ac.uk/welcome.html http://www.europractice.stfc.ac.uk/welcome.html http://cmp.imag.fr/ http://cmp.imag.fr/ http://cmp.imag.fr/products/ic/?p=prices2014 http://cmp.imag.fr/products/ic/?p=prices2014 http://cmp.imag.fr/products/ic/?p=prices2015 http://cmp.imag.fr/products/ic/?p=prices2015 http://cmp.imag.fr/products/ic/?p=prices2016 http://cmp.imag.fr/products/ic/?p=prices2016 ahh crap..."which are sent to customers upon signature of a Confidentiality and License Agreement" anyways, prices...hope that helps