5 ms·

AVX2 usage reduces clock frequency for a millisecond. It's suspicious (?) that performance numbers were given in terms of clock cycles and not wall clock time.

AVX2 usage reduces clock frequency for a millisecond. It's suspicious (?) that performance numbers were given in terms of clock cycles and not wall clock time. It might have even worse system performance impact for small messages, where one takes the AVX2 clock frequency hit for little gain.

tveita 11y ago
Cycles per byte is pretty standard for crypto algorithms, and tends to give consistent results across an architecture. It is usually measured with dynamic frequency scaling disabled. Do you have a source for use of AVX2 automatically reducing clock frequency? I found this: "Because Intel AVX instructions generally consume more power, frequency reductions can occur to keep the processor operating within TDP limits. [...] Performance of workloads optimized for Intel AVX instructions can be significantly greater than workloads that do not use Intel AVX instructions even when the processor is operating at a slightly lower frequency" Which seems to indicate that it would only trigger when you're doing a fair amount of work with it, which should be giving you a total performance benefit.
- knweiss 11y ago
  Check out the "Intel AVX Instructions Optimization" slide on http://anandtech.com/show/10158/the-intel-xeon-e5-v4-review/3 http://anandtech.com/show/10158/the-intel-xeon-e5-v4-review/.... Quote: On Haswell, one AVX instruction on one core forced all cores on the same socket to slow down their clockspeed by around 2 to 4 speed bins (-200,-400 MHz) for at least 1 ms, as AVX has a higher power requirement that reduces how much a CPU can turbo. On Broadwell, only the cores that run AVX code will be reducing their clockspeed, allowing the other cores to run at higher speeds.
  - tveita 11y ago
    Interesting, that seems to contradict the information in http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/performance-xeon-e5-v3-advanced-vector-extensions-paper.pdf http://www.intel.com/content/dam/www/public/us/en/documents/... Specifically, the FAQ says: "Will running a small number of Intel AVX instructions reduce frequency below the regular marked frequency? No, frequency will be reduced below the regular marked frequency only if a real power or thermal constraint is reached, not just due to the presence of Intel AVX instructions. Some workloads that utilize Intel AVX instructions could still achieve turbo above the marked TDP frequency."
    - semi-extrinsic 11y ago
      No, you're actually agreeing: GP says "it reduces how much a CPU can turbo", while you are pointing out "it will not reduce frequency below the regular marked frequency". Say marked freq is 3.4 and the CPU turbos to 3.9. GP is saying an AVX2 instruction will drop it from 3.9 to 3.7 or 3.5, while you're saying it won't drop it below 3.4.
booblik 11y ago
It is true for AVX too. The entire crypto in OpenSSL uses AVX/AVX2, including RSA and AES-GCM, so for crypto heavy servers, it is unlikely to ever leave AVX mode.

tveita 11y ago

Cycles per byte is pretty standard for crypto algorithms, and tends to give consistent results across an architecture. It is usually measured with dynamic frequency scaling disabled. Do you have a source for use of AVX2 automatically reducing clock frequency? I found this: "Because Intel AVX instructions generally consume more power, frequency reductions can occur to keep the processor operating within TDP limits. [...] Performance of workloads optimized for Intel AVX instructions can be significantly greater than workloads that do not use Intel AVX instructions even when the processor is operating at a slightly lower frequency" Which seems to indicate that it would only trigger when you're doing a fair amount of work with it, which should be giving you a total performance benefit.

knweiss 11y ago
Check out the "Intel AVX Instructions Optimization" slide on http://anandtech.com/show/10158/the-intel-xeon-e5-v4-review/3 http://anandtech.com/show/10158/the-intel-xeon-e5-v4-review/.... Quote: On Haswell, one AVX instruction on one core forced all cores on the same socket to slow down their clockspeed by around 2 to 4 speed bins (-200,-400 MHz) for at least 1 ms, as AVX has a higher power requirement that reduces how much a CPU can turbo. On Broadwell, only the cores that run AVX code will be reducing their clockspeed, allowing the other cores to run at higher speeds.
- tveita 11y ago
  Interesting, that seems to contradict the information in http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/performance-xeon-e5-v3-advanced-vector-extensions-paper.pdf http://www.intel.com/content/dam/www/public/us/en/documents/... Specifically, the FAQ says: "Will running a small number of Intel AVX instructions reduce frequency below the regular marked frequency? No, frequency will be reduced below the regular marked frequency only if a real power or thermal constraint is reached, not just due to the presence of Intel AVX instructions. Some workloads that utilize Intel AVX instructions could still achieve turbo above the marked TDP frequency."
  - semi-extrinsic 11y ago
    No, you're actually agreeing: GP says "it reduces how much a CPU can turbo", while you are pointing out "it will not reduce frequency below the regular marked frequency". Say marked freq is 3.4 and the CPU turbos to 3.9. GP is saying an AVX2 instruction will drop it from 3.9 to 3.7 or 3.5, while you're saying it won't drop it below 3.4.

booblik 11y ago

It is true for AVX too. The entire crypto in OpenSSL uses AVX/AVX2, including RSA and AES-GCM, so for crypto heavy servers, it is unlikely to ever leave AVX mode.