It's currently only feasible to produce very small circuits (the paper goes up to 8 gates and 3 inputs), and Cello is currently focused on a narrow class of cir

It's currently only feasible to produce very small circuits (the paper goes up to 8 gates and 3 inputs), and Cello is currently focused on a narrow class of circuits ("asynchronous combinatorial logic without feedback"). The first step of their algorithm is to convert the Verilog code into a truth table. When your circuits are so simple, I suppose it doesn't really matter what language you use to specify them, and the authors just went for whatever they thought was most convenient to parse.