4 ms·

How so? The major idea behind RISC, I thought, was to implement very few opcodes and make them very fast, which seems to me to be distinct from the question of

• userbinator 11y ago
  "make them very fast" is based on the assumption that memory can keep up with the rate at which the CPU consumes instructions. It doesn't matter whether an instruction finishes in 1 cycle or 10 if the memory can only supply one instruction every 20 cycles. A lot of people think about data accesses when talking about memory speeds, but instruction fetches are equally if not far more important to consider --- an OoO/superscalar design can "execute around" slow reads/writes if there are other non-dependent instructions, but literally can't do anything if it runs out of instructions to execute and has to wait for more to come from memory.
• Animats 11y ago
  The original claim for RISC was one instruction per clock. There are some nice simple RISC machines, especially from MIPS, which really work that way. But once CPUs got lookahead, parallelism, and went superscalar, they were doing more than one instruction per clock. This took far more transistors and complexity, but the Pentium Pro showed it could be done. It took 3000 engineers to design that CPU, and the Pentium II and III were essentially the same architecture. Now RISC was behind. Superscalar RISC machines were built. But the lower cost and design simplicity were gone. The motivation for RISC went with them. On top of that, most RISC machines padded all instructions out to the same length. Compared to x86, programs took 2x as much memory, which not only ran up cost, but required more memory bandwidth, one of the scarcest resources now that CPUs were pumping so many instructions.