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If it's Python, it's not a DSL by definition. Since you don't seem interested in addressing just one issue(I'm sure I could come up with more) around state mac
by vvanders 11y ago
If it's Python, it's not a DSL by definition.
Since you don't seem interested in addressing just one issue(I'm sure I could come up with more) around state machines I don't see any reason in continuing this discussion.
- sklogic 11y ago> If it's Python, it's not a DSL by definition. Scala is not any better. It's exactly the same kind of a eDSL - no macros, nothing, just generating objects in runtime and then serialising this tree into a Verilog code. Nothing fancy. > around state machines What state machines?!? It does not have any more features for defining FSMs than an underlying Verilog.