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My understanding is that MyHDL is in fact more like Chisel/Clash, it specifically says "It does not turn arbitrary Python into silicon" in their getting started
by kersny 11y ago
My understanding is that MyHDL is in fact more like Chisel/Clash, it specifically says "It does not turn arbitrary Python into silicon" in their getting started guide (and as sklogic says).
See also: a MyHDL UART: https://github.com/andrecp/myhdl_simple_uart/blob/master/serial_rx.py https://github.com/andrecp/myhdl_simple_uart/blob/master/ser...
- vvanders 11y agoYeah, but that feels like round hole/square peg -ish. It's like saying we've got all this stuff over here but don't use it, really, we mean don't! You're going to spend a ton of docs explaining to the user what parts of the language you can't use rather than having a DSL spec that's clear in what's supported. With a proper DSL you also don't have to massage language features that don't quite map(say enums for state machines) into a format that it's not meant for.
- sebastic 11y agoYou have no idea what you're talking about. You're wrong, MyHDL is a proper hardware DSL in Python. You've never used it and you have no idea what you're talking about