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At least it's better than Verilog. But there's Python to the rescue! http://www.myhdl.org/ http://www.myhdl.org/ Still a lot of tooling left but my FPGA tinker
by whitegrape 11y ago
At least it's better than Verilog. But there's Python to the rescue! http://www.myhdl.org/ http://www.myhdl.org/
Still a lot of tooling left but my FPGA tinkering became much more enjoyable when I stumbled across MyHDL.
- vvanders 11y agoUgh. Every time I see imperative language X adapted to RTL/VHDL/Verilog I want to slap someone. They aren't the same, gates are a fundamentally different primitives. You shouldn't be using a language built around serial actions for something that's inherently parallel. You bring all sorts of baggage along that you don't need. [edit] They don't even specify if their state machine generated is Mealy vs Moore. This is the stuff that you want control over and not abstracted away by some language that you don't know how it will synthesize.
- sklogic 11y agoYou did not get it. MyHDL is simply a macro-processor used to generate an RTL. And generating a sequence of similar, say, module instances is ok even with an imperative language, even Verilog got for loops for this. Chisel and Clash are not any different.
- vvanders 11y agoYou might want to re-read my post again, I'm specifically railing against imperative -> RTL/VHDL/Verilog. Verilog may have for loops but they're largely used for simulation, they're expensive in terms of synthesized hardware(mostly toolchain/process dependent on how they synthesize) and can only be fixed size. I've got no issue with Chisel, it's a DSL which I think is a good fit. What I'm arguing against is constructs that don't have a clear mapping to hardware representations which means you have to guess at what the compiler generates(see my Mealy vs Moore comment above).
- kersny 11y agoMy understanding is that MyHDL is in fact more like Chisel/Clash, it specifically says "It does not turn arbitrary Python into silicon" in their getting started guide (and as sklogic says). See also: a MyHDL UART: https://github.com/andrecp/myhdl_simple_uart/blob/master/serial_rx.py https://github.com/andrecp/myhdl_simple_uart/blob/master/ser...
- vvanders 11y agoYeah, but that feels like round hole/square peg -ish. It's like saying we've got all this stuff over here but don't use it, really, we mean don't! You're going to spend a ton of docs explaining to the user what parts of the language you can't use rather than having a DSL spec that's clear in what's supported. With a proper DSL you also don't have to massage language features that don't quite map(say enums for state machines) into a format that it's not meant for.
- sebastic 11y agoYou have no idea what you're talking about. You're wrong, MyHDL is a proper hardware DSL in Python. You've never used it and you have no idea what you're talking about
- sklogic 11y agoMyHDL is exactly the same kind of a eDSL as Chisel. And you have a full control of what it generates, see the examples.
- frozenport 11y agoActually Verilog developers are orders of magnitude more efficient than their VHDL counterparts. http://www.bawankule.com/verilogcenter/contest.html http://www.bawankule.com/verilogcenter/contest.html
- whitegrape 11y agoWow 1997, but thanks for the link, it was a fun read. It'd be fun to hear from people in the industry what their experience has been on larger multi-people projects -- e.g. how long would it take to create an ASIC like http://www.jandecaluwe.com/hdldesign/digmac.html http://www.jandecaluwe.com/hdldesign/digmac.html ?