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Just thinking about writing VHDL again gives me the heebie-jeebies. But this is very cool, and I love the possibilities enabled by FPGAs and OSS. However we're

• brian-armstrong 11y ago
  I've been really wanting to try Chisel https://chisel.eecs.berkeley.edu/ https://chisel.eecs.berkeley.edu/ They have a RISC V implementation in it so it can't be too bad
  • sebastic 11y ago
    Chisel doesn't help. It just converts to verilog. The verilog is then converted by a closed source program to a closed file format that is then uploaded by a closed sourced program to closed fpga hardware.
• striking 11y ago
  This open source stack may interest you, then. http://www.clifford.at/icestorm/ http://www.clifford.at/icestorm/
  • cinquemb 11y ago
    Right now for a project im using kicad, yosys, arachne-pnr and icestorm. As n00b to this layer (most exposure was through matsci and cheme req classes), its so much fun to be able to learn along the way (and i get to save $600 instead of buying someone else fpga and peripherals and getting exactly want I want i need out of it, no more or less). Although i wish i could get on with the rest of my project, this is a fun detour.
• tricky 11y ago
  oh man, VHDL was the worst. My hope is things like this will get people to build better, open sourced tooling.
  • whitegrape 11y ago
    At least it's better than Verilog. But there's Python to the rescue! http://www.myhdl.org/ http://www.myhdl.org/ Still a lot of tooling left but my FPGA tinkering became much more enjoyable when I stumbled across MyHDL.
    • vvanders 11y ago
      Ugh. Every time I see imperative language X adapted to RTL/VHDL/Verilog I want to slap someone. They aren't the same, gates are a fundamentally different primitives. You shouldn't be using a language built around serial actions for something that's inherently parallel. You bring all sorts of baggage along that you don't need. [edit] They don't even specify if their state machine generated is Mealy vs Moore. This is the stuff that you want control over and not abstracted away by some language that you don't know how it will synthesize.
      • sklogic 11y ago
        You did not get it. MyHDL is simply a macro-processor used to generate an RTL. And generating a sequence of similar, say, module instances is ok even with an imperative language, even Verilog got for loops for this. Chisel and Clash are not any different.
        • vvanders 11y ago
          You might want to re-read my post again, I'm specifically railing against imperative -> RTL/VHDL/Verilog. Verilog may have for loops but they're largely used for simulation, they're expensive in terms of synthesized hardware(mostly toolchain/process dependent on how they synthesize) and can only be fixed size. I've got no issue with Chisel, it's a DSL which I think is a good fit. What I'm arguing against is constructs that don't have a clear mapping to hardware representations which means you have to guess at what the compiler generates(see my Mealy vs Moore comment above).
          • kersny 11y ago
• wyager 11y ago
  Clash, Chisel, and Lambda-CCC are all big improvements over Verilog/VHDL.