KV would be stored in DDR memory in this case, which on an FPGA you can have many channels all working in parallel. In fact you could design a system that could

KV would be stored in DDR memory in this case, which on an FPGA you can have many channels all working in parallel. In fact you could design a system that could saturate a 10Gbps network link and give you deterministic, 1ms or less, I/O latency. That is difficult to match for a regular CPU system. You'll find that a lot of high-throughput CPU systems end up using FPGAs on PCIe cards to the same thing in order to achieve the needed performance.