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There have been FPGA-based startups before, the one that comes to mind is Bluearc (implemented TCP and NFS stacks, and a filesystem in FPGAs in a network attach
by mprovost 11y ago
There have been FPGA-based startups before, the one that comes to mind is Bluearc (implemented TCP and NFS stacks, and a filesystem in FPGAs in a network attached storage appliance, later acquired by HDS). The problem seems to be, that it takes a massive engineering effort to keep introducing new FPGA designs that are even faster. Otherwise your temporary advantage gets eaten up by Moore's law. Competitors just have to wait for Intel to introduce a new CPU and their code gets an automatic speed boost. Meanwhile their engineers are working on features. Bluearc fell behind with delays to their new models and the competition caught up in performance just by buying new motherboards. As a consumer you want some guarantee that the product you're buying will continue to be the fastest, and it's a safer bet to place on Intel than a startup.
If it's a very specific problem domain you can get a temporary advantage but you have to stay on the treadmill constantly to stay ahead. It also seems that there's a middle road that isn't often taken (possibly with the exception of gaming) where you can use assembly language (at least for performance critical sections). It's probably less difficult than designing for FPGAs and you still get a boost with new chips, assuming Intel doesn't destroy your optimisations.
- bravo22 11y agoI mostly agree with you but in the case of key/value store the problem is mostly an I/O issue, not CPU performance. It is an architectural issue. An FPGA can give you deterministic, consistent storage at very low latency -- even microseconds -- specially when network processing is done on the wire. This is the same reason a lot of deep packet inspection and do-X-with-a-packet-on-the-wire hardware is built around FPGA. Moore's law speeds up FPGAs the same as other ASICs. Newest Xilinx FPGAs are 16nm FinFET. It may not make much sense to deploy this for a small shop but at Google or AWS scale having a hardware based key/value store has many advantages.
- mprovost 11y agoThat's why I thought of Bluearc - it was a storage system so the overall throughput was ultimately limited by hard disks. The FPGAs were used to optimise all of the front end protocol and filesystem processing. I imagine the same is true of most key-value stores, at scale you're going to have to store the values somewhere slow and optimising key lookups only gains you so much. My impression of FPGAs is that yes, Moore's law does help, but at this point it's mostly by adding transistors. If your design doesn't take advantage of them, don't they just sit idle? Whereas Intel puts a lot of effort into making those extra transistors speed up even single threaded legacy code. Your example of network hardware is interesting where you can keep the whole problem domain local I imagine it's a better use case.
- bravo22 11y agoKV would be stored in DDR memory in this case, which on an FPGA you can have many channels all working in parallel. In fact you could design a system that could saturate a 10Gbps network link and give you deterministic, 1ms or less, I/O latency. That is difficult to match for a regular CPU system. You'll find that a lot of high-throughput CPU systems end up using FPGAs on PCIe cards to the same thing in order to achieve the needed performance.
- kmicklas 11y ago> It also seems that there's a middle road that isn't often taken (possibly with the exception of gaming) where you can use assembly language (at least for performance critical sections). Is using assembly really a meaningful advantage though? I think FPGAs have the advantage of being a completely different architecture which allows different algorithms with non-constant factor speedups. Assembly is going to give at most something like a constant factor 5% speedup and that's being pretty optimistic (assuming C baseline).
- cbsmith 11y agoThat's not entirely true... C imposes some basic architecture structures (heap, stack, calling conventions, etc.) which can impose non-linear efficiency costs.
- robryk 11y agoAll of those costs, except for heap allocation related ones, are roughly per-function-call costs. If a function gets inlined, an optimizer can get rid of them. Also, don't some link time optimizers help with pessimizations related to calling conventions?
- cbsmith 11y agoA sufficiently smart compiler/linker can always undo things.
- cbsmith 11y agoBlueArc is just one example, and arguably they were crushed a lot of other factors. In general, Moore's law works just as well for FPGAs as it does CPUs & ASICs. FPGA expertise is definitely in short supply, but, as an example, with HFT, you see a lot of FPGAs.
- mprovost 11y agoI'm struggling to think of other FPGA startups, do you know of any? It seems like if it were the silver bullet that it's often made out to be, then there would be more examples.