I don't really understand how it could be that problematic. It would only be an issue if there was a memory access in between the time the ptbr changes and the

I don't really understand how it could be that problematic. It would only be an issue if there was a memory access in between the time the ptbr changes and the asid changes. But the instructions for manipulating CSRs don't access memory. If you had the instructions for changing these two registers one after another, there should be no intervening memory access. This might be broken if the CPU takes an interrupt, but interrupts are generally disabled during the context switch routine.