4 ms·
Their comment about the address space identifier field in the MMU setup is absolutely golden. We need to get more practical experience using the architecture t
by brandmeyer 11y ago
Their comment about the address space identifier field in the MMU setup is absolutely golden. We need to get more practical experience using the architecture to help inform the design from other perspectives.
- zhemao 11y agoI don't really understand how it could be that problematic. It would only be an issue if there was a memory access in between the time the ptbr changes and the asid changes. But the instructions for manipulating CSRs don't access memory. If you had the instructions for changing these two registers one after another, there should be no intervening memory access. This might be broken if the CPU takes an interrupt, but interrupts are generally disabled during the context switch routine.
- brandmeyer 11y agoIn principle, the two instructions could cross a page boundary. Its a narrow corner case, but it is there.
- zhemao 11y agoOh yeah. Didn't think of that. Actually, just crossing a cache block boundary might be enough to trigger bad behavior.
- renox 11y agoI wonder what will be the performance for manupilating big numbers with RISC V (cryptography) for example, the performance will likely be very low..