5 ms·

Main take away: Intel is doing three phases instead of two tick-tocks. Secondary take away: due to the increased time to move to a better manufacturing process

by ricw 11y ago

Main take away: Intel is doing three phases instead of two tick-tocks. Secondary take away: due to the increased time to move to a better manufacturing process, Intel will likely not have as much a competitive advantage anymore. Though the number of competitors will (and has already) decrease due to the high investments. Would be interesting to see how long intel estimates the process cycles are going to be, i.e. how Moore's law will progress. Weird statement in the article: "it (TSCMs 7nm tech) should be very similar in terms of transistor density to Intel's 10-nanometer technology". This makes no sense as it would be comparing apples and pears. Surely they are referring to TSCMs 10nm tech?!

ghaff 11y ago
>Weird statement in the article At this point, process nodes don't map to a particularly well-defined set of feature sizes across vendors. So what I assume they're saying is that what Intel calls 10nm is actually pretty similar in terms of transistor size/density to what TSMC is calling 7nm. (No idea if that's actually true but it's what I believe is being said.)
- creshal 11y ago
  Yes. Node sizes and actually physical sizes have no correlation anymore. Smaller nodes are smaller, but nowhere near the sizes suggested by names. The already a decade old 45nm process highlights this nicely: https://en.wikipedia.org/wiki/45_nanometer#Technology_demos https://en.wikipedia.org/wiki/45_nanometer#Technology_demos Effective sizes are all over the place, and Intel's process in particular is nowhere near 45nm for any relevant dimension. It's similar with more recent technologies (and with 3D transistors, the distance between two arbitrary points becomes even less comparable.)
- phkahler 11y ago
  I've been wondering if EUV will bring things back in line. They say the light sources are not bright enough yet, but isn't doing a 2-4x exposure better than double or triple pattering? If the total time were the same you'd still have the benefit of the shorter wavelength allowing dramatically smaller features. What am I missing?
  - Armisael16 11y ago
    It isn't 25% as bright as it needs to be - it's more like 1% or 0.1%. The total time isn't the same.
    - Pietertje 11y ago
      That is not true at all, wafer throughput is a factor 4-5 less... The mistake in the first comment is that with self aligned double patterning you only need one litho step, not two. The same applies for SQDP. And since litho is one of the most expensive steps double patterning is more cost effective. From a technology point of view the problem with EUV is more the line edge roughness, line width roughness, defects and the reliability... Given, more light will make the job easier
deelowe 11y ago
> how Moore's law will progress. I think it's all but confirmed at this point that it's not progressing. What we're witnessing here is it's death.
- ricw 11y ago
  It certainly isn't dead. It is slower than it was before. Moore's original law stated that every 12 months the number of transistors would double. That was revised to 18 month in the 90s, and is now due another update.
  - deelowe 11y ago
    I guess we can agree to disagree on that one. Every trend we look into, we see signs of it's death from memory prices to Intel's struggles on recent chips.
    - emcq 11y ago
      Furthermore it's not a useful trend anymore if it's due for an update. What would that new constant be that people feel confident will hold over the next 10 years? Seems like quite the Frankenstein "law" to be hacking piecewise functions together. If it's not dead, it's certainly dying. Perpetual exponential growth is irrational given finite resources.
      - ant6n 11y ago
        Well, unless the factor is smaller than 1.
samfisher83 11y ago
Another reason might be they have no AMD pushing them. They are hitting physical physics barriers, but the fact they have no real competitors makes them have less incentive to push the envelope.
- skylan_q 11y ago
  It's possible, but the usual pattern is that Intel is slightly price-competitive with AMD when the CPUs are in the same range of performance, and then Intel's prices just rocket upward after that. There's no reason to not come out with an $8,000 desktop CPU if they can get more performance.
  - deleted 11y ago
    [deleted]
- maaku 11y ago
  TSMC?
TTPrograms 11y ago
I'm also willing to give the benefit of the doubt in that given how sophisticated processors have become they realized that for important use cases they can improve performance pretty significantly with primarily microcode tweaks and slight architecture changes. If that's the case then may as well do that and take more time / less cost refining the processes and architectures for the next node. I'm mostly speculating, though.
matt_d 11y ago
> Weird statement in the article: "it (TSCMs 7nm tech) should be very similar in terms of transistor density to Intel's 10-nanometer technology". This makes no sense as it would be comparing apples and pears. Surely they are referring to TSCMs 10nm tech?! Process metrics are somewhat of a marketing nature nowadays (and not as directly related to the physical properties of the fabrication process as it may seem--at least not without adjusting for the differences between vendor-specific definitions in use). Compare TSMC's 10nm to Intel's 14nm: "In the case of TSMC they follow the “Foundry” node progress whereas Intel follows more of an “IDM” node transition 40nm versus 45nm, 28nm versus 32nm and 20nm versus 22nm. At the 14nm node TSMC has also chosen to call their node 16nm where everyone else is calling it 14nm." Source: https://www.semiwiki.com/forum/content/3884-who-will-lead-10nm.html https://www.semiwiki.com/forum/content/3884-who-will-lead-10... "Although the nominal gap in process nodes between Intel and TSMC appears to be narrowing, TSMC is not likely to catch up in terms of actual Moore’s Law scaling any time soon. TSMC’s 16FF+ process delivers only 20nm scaling, so they are still a generation behind Intel’s 14nm in terms of actual die area. TSMC said that 10nm shrinks by 0.52x from 16nm, nearly identical to the 0.53x scaling that Intel achieved from 22nm to 14nm. So if they stay on schedule, in 2017 TSMC will be in production on a 10nm process that is equivalent to the 14nm technology that Intel began producing in 2Q15. At that rate, even though Intel has slipped 10nm to 2H17, they will remain at least a year ahead of TSMC." Source: http://www.eetimes.com/document.asp?doc_id=1327725 http://www.eetimes.com/document.asp?doc_id=1327725
- ISV_Damocles 11y ago
  No, there's a very simple definition for these XXnm numbers and a very good reason why they only roughly correlate with transistor density. These numbers refer to the length of the channel in the MOSFET or FinFET between the Source and Drain dopant regions. The channel is always the smallest feature the fabrication process can create, but how it's created is actually with lots of solid-state physics tricks (such as annealing to cause the dopants to spread out from where they were originally implanted, looking a lot like a physical Gaussian blur), as the original masks used to define the transistor are nowhere near that small. Depending on how small they can get the mask details (mostly an issue of optics and mask creation, now bounded primarily by the frequency of light they expose to the mask material, though interesting holographic tricks can help if they've left the laboratory phase) you can define the minimum size of the transistors, themselves. But there are other considerations like heat dissipation and the melting points of the various metals you've used that may force the transistors to be larger than what you can theoretically build. The channel length is still very important because it determines how many Coulombs of charge you need to switch the transistor on, and how long it takes to propagate a signal across the transistor. It also correlates with how much leakage current the transistor has (smaller = higher) and therefore the standby power consumption, so you do continue to make an engineering trade-off to get lower, which is also why server hardware tends to get the smallest sizes first, as they least care about idle power consumption if they're being utilized correctly. Everything I've said is about 4 years out of date, when I switched from EE back to Software Engineering for financial reasons (and also my wife is an EE so we didn't want to put all of our financial eggs in one basket), but the semiconductor industry moves so slow, and proof-of-concept fabrication techniques take so long to productionize, that I doubt this is very far off. The only thing marketing has done here is fight between each other on whether or not channel size is the number to focus on, as it benefits their corporation or not.

by ricw 11y ago

ghaff 11y ago

>Weird statement in the article At this point, process nodes don't map to a particularly well-defined set of feature sizes across vendors. So what I assume they're saying is that what Intel calls 10nm is actually pretty similar in terms of transistor size/density to what TSMC is calling 7nm. (No idea if that's actually true but it's what I believe is being said.)

creshal 11y ago
Yes. Node sizes and actually physical sizes have no correlation anymore. Smaller nodes are smaller, but nowhere near the sizes suggested by names. The already a decade old 45nm process highlights this nicely: https://en.wikipedia.org/wiki/45_nanometer#Technology_demos https://en.wikipedia.org/wiki/45_nanometer#Technology_demos Effective sizes are all over the place, and Intel's process in particular is nowhere near 45nm for any relevant dimension. It's similar with more recent technologies (and with 3D transistors, the distance between two arbitrary points becomes even less comparable.)
phkahler 11y ago
I've been wondering if EUV will bring things back in line. They say the light sources are not bright enough yet, but isn't doing a 2-4x exposure better than double or triple pattering? If the total time were the same you'd still have the benefit of the shorter wavelength allowing dramatically smaller features. What am I missing?
- Armisael16 11y ago
  It isn't 25% as bright as it needs to be - it's more like 1% or 0.1%. The total time isn't the same.
  - Pietertje 11y ago
    That is not true at all, wafer throughput is a factor 4-5 less... The mistake in the first comment is that with self aligned double patterning you only need one litho step, not two. The same applies for SQDP. And since litho is one of the most expensive steps double patterning is more cost effective. From a technology point of view the problem with EUV is more the line edge roughness, line width roughness, defects and the reliability... Given, more light will make the job easier

deelowe 11y ago

> how Moore's law will progress. I think it's all but confirmed at this point that it's not progressing. What we're witnessing here is it's death.

ricw 11y ago
It certainly isn't dead. It is slower than it was before. Moore's original law stated that every 12 months the number of transistors would double. That was revised to 18 month in the 90s, and is now due another update.
- deelowe 11y ago
  I guess we can agree to disagree on that one. Every trend we look into, we see signs of it's death from memory prices to Intel's struggles on recent chips.
  - emcq 11y ago
    Furthermore it's not a useful trend anymore if it's due for an update. What would that new constant be that people feel confident will hold over the next 10 years? Seems like quite the Frankenstein "law" to be hacking piecewise functions together. If it's not dead, it's certainly dying. Perpetual exponential growth is irrational given finite resources.
    - ant6n 11y ago
      Well, unless the factor is smaller than 1.

samfisher83 11y ago

Another reason might be they have no AMD pushing them. They are hitting physical physics barriers, but the fact they have no real competitors makes them have less incentive to push the envelope.

skylan_q 11y ago
It's possible, but the usual pattern is that Intel is slightly price-competitive with AMD when the CPUs are in the same range of performance, and then Intel's prices just rocket upward after that. There's no reason to not come out with an $8,000 desktop CPU if they can get more performance.
- deleted 11y ago
  [deleted]
maaku 11y ago
TSMC?

TTPrograms 11y ago

I'm also willing to give the benefit of the doubt in that given how sophisticated processors have become they realized that for important use cases they can improve performance pretty significantly with primarily microcode tweaks and slight architecture changes. If that's the case then may as well do that and take more time / less cost refining the processes and architectures for the next node. I'm mostly speculating, though.

matt_d 11y ago

> Weird statement in the article: "it (TSCMs 7nm tech) should be very similar in terms of transistor density to Intel's 10-nanometer technology". This makes no sense as it would be comparing apples and pears. Surely they are referring to TSCMs 10nm tech?! Process metrics are somewhat of a marketing nature nowadays (and not as directly related to the physical properties of the fabrication process as it may seem--at least not without adjusting for the differences between vendor-specific definitions in use). Compare TSMC's 10nm to Intel's 14nm: "In the case of TSMC they follow the “Foundry” node progress whereas Intel follows more of an “IDM” node transition 40nm versus 45nm, 28nm versus 32nm and 20nm versus 22nm. At the 14nm node TSMC has also chosen to call their node 16nm where everyone else is calling it 14nm." Source: https://www.semiwiki.com/forum/content/3884-who-will-lead-10nm.html https://www.semiwiki.com/forum/content/3884-who-will-lead-10... "Although the nominal gap in process nodes between Intel and TSMC appears to be narrowing, TSMC is not likely to catch up in terms of actual Moore’s Law scaling any time soon. TSMC’s 16FF+ process delivers only 20nm scaling, so they are still a generation behind Intel’s 14nm in terms of actual die area. TSMC said that 10nm shrinks by 0.52x from 16nm, nearly identical to the 0.53x scaling that Intel achieved from 22nm to 14nm. So if they stay on schedule, in 2017 TSMC will be in production on a 10nm process that is equivalent to the 14nm technology that Intel began producing in 2Q15. At that rate, even though Intel has slipped 10nm to 2H17, they will remain at least a year ahead of TSMC." Source: http://www.eetimes.com/document.asp?doc_id=1327725 http://www.eetimes.com/document.asp?doc_id=1327725

ISV_Damocles 11y ago
No, there's a very simple definition for these XXnm numbers and a very good reason why they only roughly correlate with transistor density. These numbers refer to the length of the channel in the MOSFET or FinFET between the Source and Drain dopant regions. The channel is always the smallest feature the fabrication process can create, but how it's created is actually with lots of solid-state physics tricks (such as annealing to cause the dopants to spread out from where they were originally implanted, looking a lot like a physical Gaussian blur), as the original masks used to define the transistor are nowhere near that small. Depending on how small they can get the mask details (mostly an issue of optics and mask creation, now bounded primarily by the frequency of light they expose to the mask material, though interesting holographic tricks can help if they've left the laboratory phase) you can define the minimum size of the transistors, themselves. But there are other considerations like heat dissipation and the melting points of the various metals you've used that may force the transistors to be larger than what you can theoretically build. The channel length is still very important because it determines how many Coulombs of charge you need to switch the transistor on, and how long it takes to propagate a signal across the transistor. It also correlates with how much leakage current the transistor has (smaller = higher) and therefore the standby power consumption, so you do continue to make an engineering trade-off to get lower, which is also why server hardware tends to get the smallest sizes first, as they least care about idle power consumption if they're being utilized correctly. Everything I've said is about 4 years out of date, when I switched from EE back to Software Engineering for financial reasons (and also my wife is an EE so we didn't want to put all of our financial eggs in one basket), but the semiconductor industry moves so slow, and proof-of-concept fabrication techniques take so long to productionize, that I doubt this is very far off. The only thing marketing has done here is fight between each other on whether or not channel size is the number to focus on, as it benefits their corporation or not.