This is the master plan, but replace x86 with RISC-V to make it more efficient. It's impractical for economical reasons to backdoor the FPGA (where's the IO?

This is the master plan, but replace x86 with RISC-V to make it more efficient. It's impractical for economical reasons to backdoor the FPGA (where's the IO? You don't know.) nor the compiler (Hey, all I see is a netlist, my AI isn't that clever).