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HDL is a very different paradigm than Javascript. You aren't writing a program. You are describing hardware which is why it is synthesized into gates and not co
by bravo22 11y ago
HDL is a very different paradigm than Javascript. You aren't writing a program. You are describing hardware which is why it is synthesized into gates and not compiled. They are apples and oranges. The closest analog I can think of is vector graphics vs raster graphics, i.e. Adobe Illustrator vs Photoshop. They're meant for different purposes.
Verilog/SystemVerilog are pretty great at what they do. People are pretty happy with them. The problem is those who get into FPGA (from CS background) expect to write "code" which isn't what you are doing in the hardware world.
There is also SystemC when you want to write test benches, or Bus-Functional-Models. Those is also used pretty extensively in the hardware flow.
- pjc50 11y agoYou don't have to mansplain HDL to me. I agree that writing code will lead you astray, but not with "people are pretty happy with Verilog". It has a whole load of limitations: no aggregate types, no language-level distinction between synthesisable and unsynthesisable, and quasi-sequentialism that confuses beginners.
- TrevorJ 11y ago>mansplain Really?
- bravo22 11y agoSystemVerilog supports structs and unions. Synthesizable constructs are up to the synthesis tool to infer, and they are very clear as to how they work. Any HDL language will be confusing to someone who isn't used it because you are defining a set of parallel behaviours and responses to specific stimulus and not a set of instructions. There can always be improvements but as of today Sys/Verilog is the most popular by far, followed by VHDL. Therefore the tool vendors support those languages which is what I was responding in the original post.