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(a) you don't have to use any vendor's IDE, only their placement and synthesis tools which all support command line (b) Verilog and VHDL are the only two domina

by bravo22 11y ago

(a) you don't have to use any vendor's IDE, only their placement and synthesis tools which all support command line (b) Verilog and VHDL are the only two dominant HDL languages.. what other language would you want to program in??

HanW 11y ago
b) Bluespec
- bravo22 11y ago
  Bluespec is SystemVerilog extensions, so it still falls under Verilog support. Bluespec compiler spits out Verilog RTL for it to be fed into other tools, like Xilinx's synthesizer. So yes you can use Bluespec with Xilinx/Altera tools today. It also is new and thus not known and used by thousands of RTL coders everyday.
- deleted 11y ago
  [deleted]
pjc50 11y ago
I'd quite like to see some HDL innovation. You can compile to Verilog just like people compile to Javascript to run in the browser, but it's not the most convenient way of doing it.
- bravo22 11y ago
  HDL is a very different paradigm than Javascript. You aren't writing a program. You are describing hardware which is why it is synthesized into gates and not compiled. They are apples and oranges. The closest analog I can think of is vector graphics vs raster graphics, i.e. Adobe Illustrator vs Photoshop. They're meant for different purposes. Verilog/SystemVerilog are pretty great at what they do. People are pretty happy with them. The problem is those who get into FPGA (from CS background) expect to write "code" which isn't what you are doing in the hardware world. There is also SystemC when you want to write test benches, or Bus-Functional-Models. Those is also used pretty extensively in the hardware flow.
  - pjc50 11y ago
    You don't have to mansplain HDL to me. I agree that writing code will lead you astray, but not with "people are pretty happy with Verilog". It has a whole load of limitations: no aggregate types, no language-level distinction between synthesisable and unsynthesisable, and quasi-sequentialism that confuses beginners.
    - TrevorJ 11y ago
      >mansplain Really?
    - bravo22 11y ago
      SystemVerilog supports structs and unions. Synthesizable constructs are up to the synthesis tool to infer, and they are very clear as to how they work. Any HDL language will be confusing to someone who isn't used it because you are defining a set of parallel behaviours and responses to specific stimulus and not a set of instructions. There can always be improvements but as of today Sys/Verilog is the most popular by far, followed by VHDL. Therefore the tool vendors support those languages which is what I was responding in the original post.

by bravo22 11y ago

HanW 11y ago

b) Bluespec

bravo22 11y ago
Bluespec is SystemVerilog extensions, so it still falls under Verilog support. Bluespec compiler spits out Verilog RTL for it to be fed into other tools, like Xilinx's synthesizer. So yes you can use Bluespec with Xilinx/Altera tools today. It also is new and thus not known and used by thousands of RTL coders everyday.
deleted 11y ago
[deleted]

pjc50 11y ago

I'd quite like to see some HDL innovation. You can compile to Verilog just like people compile to Javascript to run in the browser, but it's not the most convenient way of doing it.

bravo22 11y ago
HDL is a very different paradigm than Javascript. You aren't writing a program. You are describing hardware which is why it is synthesized into gates and not compiled. They are apples and oranges. The closest analog I can think of is vector graphics vs raster graphics, i.e. Adobe Illustrator vs Photoshop. They're meant for different purposes. Verilog/SystemVerilog are pretty great at what they do. People are pretty happy with them. The problem is those who get into FPGA (from CS background) expect to write "code" which isn't what you are doing in the hardware world. There is also SystemC when you want to write test benches, or Bus-Functional-Models. Those is also used pretty extensively in the hardware flow.
- pjc50 11y ago
  You don't have to mansplain HDL to me. I agree that writing code will lead you astray, but not with "people are pretty happy with Verilog". It has a whole load of limitations: no aggregate types, no language-level distinction between synthesisable and unsynthesisable, and quasi-sequentialism that confuses beginners.
  - TrevorJ 11y ago
    >mansplain Really?
  - bravo22 11y ago
    SystemVerilog supports structs and unions. Synthesizable constructs are up to the synthesis tool to infer, and they are very clear as to how they work. Any HDL language will be confusing to someone who isn't used it because you are defining a set of parallel behaviours and responses to specific stimulus and not a set of instructions. There can always be improvements but as of today Sys/Verilog is the most popular by far, followed by VHDL. Therefore the tool vendors support those languages which is what I was responding in the original post.