> Could you design a language which do a JIT style compilation to data flow calculations, by creating some arithmethic and logical functions onto a FPGA? The c

> Could you design a language which do a JIT style compilation to data flow calculations, by creating some arithmethic and logical functions onto a FPGA? The complete compilation process (source code --> netlist --> mapped design --> placed & routed design) can take several hours for large designs; maybe several minutes for small designs. Not suitable for JIT.