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In the projects where I use them in university I always found them quite hard to work with. While the idea of programming them with VHDL or Verilog is quite st
by kutkloon7 11y ago
In the projects where I use them in university I always found them quite hard to work with.
While the idea of programming them with VHDL or Verilog is quite straightforward, there were a lot of bumps in the road to getting a working design. Specialized tools which generate reports that go on for pages and pages (our team was completely unable to do something about the path of longest delay), complicated information about the clock, and having to work with vague documentation and intellectual property.
FPGA's are really nice when they work, but I feel like they are just too complicated for developers to get started with on their own, at the moment.
- makomk 11y agoYeah, they're a bit of a dark art. They require hardware design tricks like pipelining for best performance, you can run into fun stuff like routing fabric congestion which absolutely kills performance and in turn is affected by stuff like the layout the tools choose and whether you're using cheaper or more expensive FPGAs (which at least for Xilinx have very different balances of routing resources), etc. I've seen timing failures due to the signals having to divert around the clock generators at the edge of the chip, which were effectively a wedge with no routing fabric in between two sections of logic.