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Risc-V is going to support tagged memory.
by justincormack 11y ago
Risc-V is going to support tagged memory.
- hga 11y agoAs far as I know, that's only the plan of the lowRISC project that's using RISC-V: http://www.lowrisc.org/ http://www.lowrisc.org/
- nickpsecurity 11y agoThat's actually meaningless without context. Reason is tags are used to fo all kinds of things in tagged CPU's. Some have almost no safety while some support arbitrary security policies. So, we have to wait and see for each individual implementation. Far as safe/secure, look at crash-safe.org for best in class of those. SAFE architecture isn't just tagged: it's holistic in addressing security & SW dev issues at each layer. Actually, they might be trying to do too much haha. Told people they should've just ported Oberon or Java to the CPU to give us interim solution.