3 ms·
For dram reads, to my knowledge you can't read only 64kb anyway. You get much larger pages from dram.
by sliverstorm 11y ago
For dram reads, to my knowledge you can't read only 64kb anyway. You get much larger pages from dram.
- mattgodbolt 11y agoDRAM pages are indeed larger; but a single bus transaction does not have to read the whole DRAM page. Tons more info here: https://www.akkadia.org/drepper/cpumemory.pdf https://www.akkadia.org/drepper/cpumemory.pdf
- vardump 11y ago> For dram reads, to my knowledge you can't read only 64kb anyway. You get much larger pages from dram. I didn't say 64 kB, I said 64 bytes is the read and store transaction size. I think DRAM page sizes are 2^n * 512 bytes, where n is a positive small integer. Typical DRAM bank sizes are 512 bytes, 1 kB or 2 kB. So, with interleaved memory channels DRAM page changes every (DRAM page size) * (number of memory channels). I think typical bank switch intervals for a laptop with 2 memory channels is every 1 (DDR4 minimum), 2 (DDR3 minimum, probably typical) or 4 kB. Although DRAM bank sizes are irrelevant in this context. I was talking about the smallest possible cached DRAM transaction -- read or store. Which is the same as the cache line size, 64 bytes. Simplified: Read 1 byte from memory and the CPU will fetch 64 bytes. Write 1 byte to memory and the CPU will first fetch 64 bytes (RFO), modify the cache line and eventually when the cache line is evicted (which can be quite a while) write 64 bytes back.